First pass at a Verilog Backend. Not tested, but compiles and generates reasonable verilog. Requires inlining, future versions will instantiate modules

1 files changed, 26 insertions, 1 deletions

diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 33b64b8b..e912d3a0 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -4,12 +4,12 @@ defpackage firrtl/compiler :
   import firrtl/passes
   import firrtl/errors
   import firrtl/flo
+  import firrtl/verilog
   import firrtl/ir2
   import firrtl/ir-utils
 
 public defstruct StandardFlo <: Compiler :
    file: String with: (as-method => true)
-
 public defmethod passes (c:StandardFlo) -> List<Pass> :
    to-list $ [
       CheckHighForm()
@@ -33,6 +33,31 @@ public defmethod passes (c:StandardFlo) -> List<Pass> :
       Flo(file(c))
    ]
 
+public defstruct StandardVerilog <: Compiler :
+   file: String with: (as-method => true)
+public defmethod passes (c:StandardVerilog) -> List<Pass> :
+   to-list $ [
+      CheckHighForm()
+      TempElimination()
+      ToWorkingIR()
+      MakeExplicitReset()
+      ResolveKinds()
+      CheckKinds()
+      InferTypes()
+      CheckTypes()
+      ResolveGenders()
+      CheckGenders()
+      ExpandAccessors()
+      LowerToGround()
+      ExpandIndexedConnects()
+      ExpandWhens()
+      InferWidths()
+      Inline()
+      SplitExp()
+      ToRealIR()
+      Verilog(file(c))
+   ]
+
 ;============= DRIVER ======================================
 public defn run-passes (c:Circuit,comp:Compiler) : 
    run-passes(c,passes(comp))