The transformation works! Kind of, it works fine when everything is alwasy ready, has some weird issues when they're not, but also kind of works in that the hardware verifier still reports the right answer, it seems to go to half duty cycle and then do every token twice

2 files changed, 11 insertions, 3 deletions

diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala
index ce8d2b1d..e8ad8d56 100644
--- a/src/main/scala/firrtl/Driver.scala
+++ b/src/main/scala/firrtl/Driver.scala
@@ -83,9 +83,9 @@ object Driver
     writer.write(ast3.serialize())
     writer.close()
     
-    //val postCmd = Seq("firrtl-stanza", "-i", temp2, "-o", output, "-b", "firrtl") ++ stanzaPostTransform.flatMap(Seq("-x", _))
-    //println(postCmd.mkString(" "))
-    //postCmd.!
+    val postCmd = Seq("firrtl-stanza", "-i", temp2, "-o", output, "-X", "verilog")
+    println(postCmd.mkString(" "))
+    postCmd.!
   }
 
   private def verilog(input: String, output: String)(implicit logger: Logger)
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 73799765..d767f027 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -196,6 +196,13 @@ object Utils {
       } 
       s + debug(dir)
     }
+    def flip(): FieldDir = {
+      dir match {
+        case Reverse => Default
+        case Default => Reverse
+      }
+    }
+        
     def toPortDir(): PortDir = {
       dir match {
         case Default => Output
@@ -207,6 +214,7 @@ object Utils {
   implicit class FieldUtils(field: Field) {
     def serialize(implicit flags: FlagMap = FlagMap): String = 
       s"${field.dir.serialize} ${field.name} : ${field.tpe.serialize}" + debug(field)
+    def flip(): Field = Field(field.name, field.dir.flip, field.tpe)
 
     def getType(): Type = field.tpe
     def toPort(): Port = Port(NoInfo, field.name, field.dir.toPortDir, field.tpe)