Added fame transformation and new package, making progress

2 files changed, 21 insertions, 61 deletions

diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala
index 067ad4f4..c748f92e 100644
--- a/src/main/scala/firrtl/Driver.scala
+++ b/src/main/scala/firrtl/Driver.scala
@@ -6,6 +6,7 @@ import java.nio.file.{Paths, Files}
 import Utils._
 import DebugUtils._
 import Passes._
+import midas.Fame1
 
 object Driver
 {
@@ -39,10 +40,15 @@ object Driver
 
   def toVerilogWithFame(input: String, output: String)
   {
+    val logger = Logger(new PrintWriter(System.err, true))
+
     val stanzaPreTransform = List("rem-spec-chars", "high-form-check",
       "temp-elim", "to-working-ir", "resolve-kinds", "infer-types",
       "resolve-genders", "check-genders", "check-kinds", "check-types",
-      "expand-accessors", "lower-to-ground", "inline-indexers")
+      "expand-accessors", "lower-to-ground", "inline-indexers", "infer-types",
+      "check-genders", "expand-whens", "infer-widths", "real-ir", "width-check",
+      "pad-widths", "const-prop", "split-expressions", "width-check",
+      "high-form-check", "low-form-check", "check-init")
     val stanzaPostTransform = List("rem-spec-chars", "high-form-check",
       "temp-elim", "to-working-ir", "resolve-kinds", "infer-types",
       "resolve-genders", "check-genders", "check-kinds", "check-types",
@@ -51,18 +57,29 @@ object Driver
       "pad-widths", "const-prop", "split-expressions", "width-check",
       "high-form-check", "low-form-check", "check-init")
 
+    //// Don't lower
+    //val temp1 = genTempFilename(input)
+    //val ast = Parser.parse(input)
+    //val writer = new PrintWriter(new File(temp1))
+    //val ast2 = fame1Transform(ast)
+    //writer.write(ast2.serialize())
+    //writer.close()
+
     // Lower-to-Ground with Stanza FIRRTL
     val temp1 = genTempFilename(input)
     val preCmd = Seq("firrtl-stanza", "-i", input, "-o", temp1, "-b", "firrtl") ++ stanzaPreTransform.flatMap(Seq("-x", _))
     println(preCmd.mkString(" "))
     preCmd.!
+
+    // Read in and execute infer-types
+    val ast = Parser.parse(temp1)
+    val ast2 = inferTypes(ast)(logger)
    
     // FAME-1 Transformation
     val temp2 = genTempFilename(input)
-    val ast = Parser.parse(temp1)
     val writer = new PrintWriter(new File(temp2))
-    val ast2 = fame1Transform(ast)
-    writer.write(ast2.serialize())
+    val ast3 = Fame1.transform(ast2)
+    writer.write(ast3.serialize())
     writer.close()
     
     //val postCmd = Seq("firrtl-stanza", "-i", temp2, "-o", output, "-b", "firrtl") ++ stanzaPostTransform.flatMap(Seq("-x", _))
diff --git a/src/main/scala/firrtl/Passes.scala b/src/main/scala/firrtl/Passes.scala
index a76c3103..39e6b64e 100644
--- a/src/main/scala/firrtl/Passes.scala
+++ b/src/main/scala/firrtl/Passes.scala
@@ -99,61 +99,4 @@ object Passes {
     Circuit(c.info, c.name, c.modules.map(inferTypes(typeMap, _)))
   }
 
-  /** FAME-1
-   *
-   *  This pass takes a lowered-to-ground circuit and performs a 
-   *    FAME-1 (Decoupled) transformation to the circuit
-   *
-   *  TODO
-   *   - SWITCH TO USING HIGH-LEVEL FIRRTL SO WE CAN MAINTAIN STRUCTURE OF BUNDLES
-   *   - Add midas$fire : indicates when the module can operate
-   *   - Add transform on each assignment to inputs/outputs to assign to data part of bundle
-   *   - Add enable logic for each register
-   *      * This should just be a when not(midas$fire) : reg := reg
-   *        At bottom of module
-   *   - QUESTIONS
-   *      * Should we have Reset be a special Type?
-   *
-   *  NOTES
-   *    - How do output consumes tie in to MIDAS fire? If all of our outputs are not consumed
-   *      in a given cycle, do we block midas$fire on the next cycle? Perhaps there should be 
-   *      a register for not having consumed all outputs last cycle
-   *    - If our outputs are not consumed we also need to be sure not to consume out inputs,
-   *      so the logic for this must depend on the previous cycle being consumed as well
-   *    - We also need a way to determine the difference between the MIDAS modules and their
-   *      connecting Queues, perhaps they should be MIDAS queues, which then perhaps prints
-   *      out a listing of all queues so that they can be properly transformed
-   *        * What do these MIDAS queues look like since we're enforcing true decoupled 
-   *          interfaces?
-   */
-  private type PortMap = Map[String, Port]
-  //private val PortMap = Map[String, Type]().withDefaultValue(UnknownType)
-  private val f1TAvail = Field("avail", Default, UIntType(IntWidth(1)))
-  private val f1TConsume = Field("consume", Reverse, UIntType(IntWidth(1)))
-  private def fame1Transform(p: Port): Port = {
-    if( p.name == "reset" ) p // omit reset
-    else {
-      p.tpe match {
-        case ClockType => p // Omit clocktype
-        case t: BundleType => throw new Exception("Bundle Types not supported in FAME-1 Transformation!")
-        case t: VectorType => throw new Exception("Vector Types not supported in FAME-1 Transformation!")
-        case t: Type => {
-            Port(p.info, p.name, p.dir, BundleType(
-                  Seq(f1TAvail, f1TConsume, Field("data", Default, t)))
-                )
-        }
-      }
-    }
-  }
-  private def fame1Transform(m: Module): Module = {
-    println("fame1Transform called on module " + m.name)
-    val ports = m.ports.map(fame1Transform)
-    val portMap = Map(ports.map(p => (p.name, p)))
-    println(portMap)
-    Module(m.info, m.name, ports, m.stmt)
-  }
-  def fame1Transform(c: Circuit): Circuit = {
-    Circuit(c.info, c.name, c.modules.map(fame1Transform))
-  }
-
 }