Changing simwrapper to group ports that go to different places, not quite there yet. Will allow simple bulk connecting at top-level

3 files changed, 38 insertions, 22 deletions

diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala
index 5eb4e9e6..1e7c4ced 100644
--- a/src/main/scala/firrtl/IR.scala
+++ b/src/main/scala/firrtl/IR.scala
@@ -1,6 +1,6 @@
 
 /* TODO
- *  - Should FileInfo be a FIRRTL node?
+ *  - Should Info be a FIRRTL node?
  *
  */
 
@@ -9,7 +9,9 @@ package firrtl
 import scala.collection.Seq
 
 // Should this be defined elsewhere?
-case class FileInfo(file: String, line: Int, column: Int) {
+trait Info
+case object NoInfo extends Info
+case class FileInfo(file: String, line: Int, column: Int) extends Info {
   override def toString(): String = s"$file@$line.$column"
 }
 
@@ -72,18 +74,18 @@ case object Write extends AccessorDir
 case object RdWr extends AccessorDir
 
 trait Stmt extends AST
-case class DefWire(info: FileInfo, name: String, tpe: Type) extends Stmt
-case class DefReg(info: FileInfo, name: String, tpe: Type, clock: Exp, reset: Exp) extends Stmt
-case class DefMemory(info: FileInfo, name: String, seq: Boolean, tpe: Type, clock: Exp) extends Stmt
-case class DefInst(info: FileInfo, name: String, module: Exp) extends Stmt 
-case class DefNode(info: FileInfo, name: String, value: Exp) extends Stmt
-case class DefPoison(info: FileInfo, name: String, tpe: Type) extends Stmt
-case class DefAccessor(info: FileInfo, name: String, dir: AccessorDir, source: Exp, index: Exp) extends Stmt
-case class OnReset(info: FileInfo, lhs: Exp, rhs: Exp) extends Stmt
-case class Connect(info: FileInfo, lhs: Exp, rhs: Exp) extends Stmt
-case class BulkConnect(info: FileInfo, lhs: Exp, rhs: Exp) extends Stmt
-case class When(info: FileInfo, pred: Exp, conseq: Stmt, alt: Stmt) extends Stmt
-case class Assert(info: FileInfo, pred: Exp) extends Stmt
+case class DefWire(info: Info, name: String, tpe: Type) extends Stmt
+case class DefReg(info: Info, name: String, tpe: Type, clock: Exp, reset: Exp) extends Stmt
+case class DefMemory(info: Info, name: String, seq: Boolean, tpe: Type, clock: Exp) extends Stmt
+case class DefInst(info: Info, name: String, module: Exp) extends Stmt 
+case class DefNode(info: Info, name: String, value: Exp) extends Stmt
+case class DefPoison(info: Info, name: String, tpe: Type) extends Stmt
+case class DefAccessor(info: Info, name: String, dir: AccessorDir, source: Exp, index: Exp) extends Stmt
+case class OnReset(info: Info, lhs: Exp, rhs: Exp) extends Stmt
+case class Connect(info: Info, lhs: Exp, rhs: Exp) extends Stmt
+case class BulkConnect(info: Info, lhs: Exp, rhs: Exp) extends Stmt
+case class When(info: Info, pred: Exp, conseq: Stmt, alt: Stmt) extends Stmt
+case class Assert(info: Info, pred: Exp) extends Stmt
 case class Block(stmts: Seq[Stmt]) extends Stmt
 case object EmptyStmt extends Stmt
 
@@ -109,10 +111,10 @@ trait PortDir extends AST
 case object Input extends PortDir
 case object Output extends PortDir
 
-case class Port(info: FileInfo, name: String, dir: PortDir, tpe: Type) extends AST
+case class Port(info: Info, name: String, dir: PortDir, tpe: Type) extends AST
 
-case class Module(info: FileInfo, name: String, ports: Seq[Port], stmt: Stmt) extends AST
+case class Module(info: Info, name: String, ports: Seq[Port], stmt: Stmt) extends AST
 
-case class Circuit(info: FileInfo, name: String, modules: Seq[Module]) extends AST
+case class Circuit(info: Info, name: String, modules: Seq[Module]) extends AST
 
 
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 4220e07f..73799765 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -196,6 +196,12 @@ object Utils {
       } 
       s + debug(dir)
     }
+    def toPortDir(): PortDir = {
+      dir match {
+        case Default => Output
+        case Reverse => Input
+      }
+    }
   }
 
   implicit class FieldUtils(field: Field) {
@@ -203,6 +209,7 @@ object Utils {
       s"${field.dir.serialize} ${field.name} : ${field.tpe.serialize}" + debug(field)
 
     def getType(): Type = field.tpe
+    def toPort(): Port = Port(NoInfo, field.name, field.dir.toPortDir, field.tpe)
   }
 
   implicit class TypeUtils(t: Type) {
@@ -242,12 +249,19 @@ object Utils {
       } 
       s + debug(p)
     }
+    def toFieldDir(): FieldDir = {
+      p match {
+        case Input => Reverse
+        case Output => Default
+      }
+    }
   }
 
   implicit class PortUtils(p: Port) {
     def serialize(implicit flags: FlagMap = FlagMap): String = 
       s"${p.dir.serialize} ${p.name} : ${p.tpe.serialize}" + debug(p)
     def getType(): Type = p.tpe
+    def toField(): Field = Field(p.name, p.dir.toFieldDir, p.tpe)
   }
 
   implicit class ModuleUtils(m: Module) {
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index 7d54ca1a..d5220206 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -39,17 +39,17 @@ class Visitor(val fullFilename: String) extends FIRRTLBaseVisitor[AST]
       case  _  => throw new Exception("Invalid String for conversion to BigInt " + s)
     }
   }
-  private def getFileInfo(ctx: ParserRuleContext): FileInfo = 
+  private def getInfo(ctx: ParserRuleContext): Info = 
     FileInfo(filename, ctx.getStart().getLine(), ctx.getStart().getCharPositionInLine())
 
 	private def visitCircuit[AST](ctx: FIRRTLParser.CircuitContext): Circuit = 
-    Circuit(getFileInfo(ctx), ctx.id.getText, ctx.module.map(visitModule)) 
+    Circuit(getInfo(ctx), ctx.id.getText, ctx.module.map(visitModule)) 
     
   private def visitModule[AST](ctx: FIRRTLParser.ModuleContext): Module = 
-    Module(getFileInfo(ctx), ctx.id.getText, ctx.port.map(visitPort), visitBlockStmt(ctx.blockStmt))
+    Module(getInfo(ctx), ctx.id.getText, ctx.port.map(visitPort), visitBlockStmt(ctx.blockStmt))
 
 	private def visitPort[AST](ctx: FIRRTLParser.PortContext): Port = 
-    Port(getFileInfo(ctx), ctx.id.getText, visitPortKind(ctx.portKind), visitType(ctx.`type`))
+    Port(getInfo(ctx), ctx.id.getText, visitPortKind(ctx.portKind), visitType(ctx.`type`))
   
 	private def visitPortKind[AST](ctx: FIRRTLParser.PortKindContext): PortDir =
     ctx.getText match {
@@ -91,7 +91,7 @@ class Visitor(val fullFilename: String) extends FIRRTLBaseVisitor[AST]
     Block(ctx.stmt.map(visitStmt)) 
 
 	private def visitStmt[AST](ctx: FIRRTLParser.StmtContext): Stmt = {
-    val info = getFileInfo(ctx)
+    val info = getInfo(ctx)
 
     ctx.getChild(0).getText match {
       case "wire" => DefWire(info, ctx.id(0).getText, visitType(ctx.`type`))