diff options
| author | Jack Koenig | 2018-10-31 14:33:29 -0700 |
|---|---|---|
| committer | Jack Koenig | 2018-10-31 15:22:26 -0700 |
| commit | 8d599182114306f77d098ba7effa836328b1e802 (patch) | |
| tree | 3de2575b57b66fbd99239e565f9f9d69283809d9 /src/main/scala/firrtl/transforms | |
| parent | bd6065b07b2c4de8cbb127a962bbfb8507f049c3 (diff) | |
Use Vector instead of List for bulk renaming in RenameMap
Diffstat (limited to 'src/main/scala/firrtl/transforms')
| -rw-r--r-- | src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala index 05fd0228..66e39e53 100644 --- a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala +++ b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala @@ -65,9 +65,9 @@ class RemoveKeywordCollisions(keywords: Set[String]) extends Transform { } namedx match { - case ComponentName(n, _) :: Nil => n - case ModuleName(n, _) :: Nil => n - case CircuitName(n) :: Nil => n + case Seq(ComponentName(n, _)) => n + case Seq(ModuleName(n, _)) => n + case Seq(CircuitName(n)) => n case x => throw new PassException( s"Verilog renaming shouldn't result in multiple renames, but found '$named -> $namedx'") } @@ -189,7 +189,7 @@ class RemoveKeywordCollisions(keywords: Set[String]) extends Transform { // Rename the circuit if the top module was renamed val mainx = renames.get(ModuleName(c.main, CircuitName(c.main))) match { - case Some(ModuleName(m, _) :: Nil) => + case Some(Seq(ModuleName(m, _))) => renames.rename(CircuitName(c.main), CircuitName(m)) m case x@ Some(_) => throw new PassException( |