Replace Mappers with Foreachers in several passes (#954)

1 files changed, 8 insertions, 16 deletions

diff --git a/src/main/scala/firrtl/transforms/CheckCombLoops.scala b/src/main/scala/firrtl/transforms/CheckCombLoops.scala
index 1a5861c5..7afce210 100644
--- a/src/main/scala/firrtl/transforms/CheckCombLoops.scala
+++ b/src/main/scala/firrtl/transforms/CheckCombLoops.scala
@@ -10,7 +10,7 @@ import annotation.tailrec
 import firrtl._
 import firrtl.ir._
 import firrtl.passes.{Errors, PassException}
-import firrtl.Mappers._
+import firrtl.traversals.Foreachers._
 import firrtl.annotations._
 import firrtl.Utils.throwInternalError
 import firrtl.graph.{MutableDiGraph,DiGraph}
@@ -86,21 +86,15 @@ class CheckCombLoops extends Transform with RegisteredTransform {
   }
 
 
-  private def getExprDeps(deps: MutableDiGraph[LogicNode], v: LogicNode)(e: Expression): Expression = e match {
-    case r: WRef =>
-      deps.addEdgeIfValid(v, toLogicNode(r))
-      r
-    case s: WSubField =>
-      deps.addEdgeIfValid(v, toLogicNode(s))
-      s
-    case _ =>
-      e map getExprDeps(deps, v)
+  private def getExprDeps(deps: MutableDiGraph[LogicNode], v: LogicNode)(e: Expression): Unit = e match {
+    case r: WRef => deps.addEdgeIfValid(v, toLogicNode(r))
+    case s: WSubField => deps.addEdgeIfValid(v, toLogicNode(s))
+    case _ => e.foreach(getExprDeps(deps, v))
   }
 
   private def getStmtDeps(
     simplifiedModules: mutable.Map[String,DiGraph[LogicNode]],
-    deps: MutableDiGraph[LogicNode])(s: Statement): Statement = {
-    s match {
+    deps: MutableDiGraph[LogicNode])(s: Statement): Unit = s match {
       case Connect(_,loc,expr) =>
         val lhs = toLogicNode(loc)
         if (deps.contains(lhs)) {
@@ -123,9 +117,7 @@ class CheckCombLoops extends Transform with RegisteredTransform {
         iGraph.getVertices.foreach(deps.addVertex(_))
         iGraph.getVertices.foreach({ v => iGraph.getEdges(v).foreach { deps.addEdge(v,_) } })
       case _ =>
-        s map getStmtDeps(simplifiedModules,deps)
-    }
-    s
+        s.foreach(getStmtDeps(simplifiedModules,deps))
   }
 
   /*
@@ -211,7 +203,7 @@ class CheckCombLoops extends Transform with RegisteredTransform {
     for (m <- topoSortedModules) {
       val internalDeps = new MutableDiGraph[LogicNode]
       m.ports.foreach({ p => internalDeps.addVertex(LogicNode(p.name)) })
-      m map getStmtDeps(simplifiedModuleGraphs, internalDeps)
+      m.foreach(getStmtDeps(simplifiedModuleGraphs, internalDeps))
       val moduleGraph = DiGraph(internalDeps)
       moduleGraphs(m.name) = moduleGraph
       simplifiedModuleGraphs(m.name) = moduleGraphs(m.name).simplify((m.ports map { p => LogicNode(p.name) }).toSet)