diff options
| author | Aditya Naik | 2024-05-29 16:57:13 -0700 |
|---|---|---|
| committer | Aditya Naik | 2024-05-29 16:57:13 -0700 |
| commit | 165804ee58cb18443042b9655328278434ddedf4 (patch) | |
| tree | 4e167eff9e7b3ec09d73dbd9feaa6f9964cd8a68 /src/main/scala/firrtl/transforms/TopWiring.scala | |
| parent | 57b8a395ee8d5fdabb2deed3db7d0c644f0a7eed (diff) | |
Add Scala3 support
Diffstat (limited to 'src/main/scala/firrtl/transforms/TopWiring.scala')
| -rw-r--r-- | src/main/scala/firrtl/transforms/TopWiring.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/TopWiring.scala b/src/main/scala/firrtl/transforms/TopWiring.scala index 9fc40c59..abab471a 100644 --- a/src/main/scala/firrtl/transforms/TopWiring.scala +++ b/src/main/scala/firrtl/transforms/TopWiring.scala @@ -151,7 +151,7 @@ class TopWiringTransform extends Transform with DependencyAPIMigration { // Map of component name to relative instance paths that result in a debug wire val sourcemods: mutable.Map[String, Seq[(ComponentName, Type, Boolean, InstPath, String)]] = - mutable.Map(sSourcesModNames.map(_ -> Seq()): _*) + mutable.Map(sSourcesModNames.map(_ -> Seq())*) state.circuit.modules.foreach { m => m.map(getSourceTypes(sSourcesNames, sourcemods, ModuleName(m.name, CircuitName(state.circuit.main)), state)) |