All of src/ formatted with scalafmt

1 files changed, 27 insertions, 22 deletions

diff --git a/src/main/scala/firrtl/transforms/RemoveWires.scala b/src/main/scala/firrtl/transforms/RemoveWires.scala
index f692e513..31fa3b6f 100644
--- a/src/main/scala/firrtl/transforms/RemoveWires.scala
+++ b/src/main/scala/firrtl/transforms/RemoveWires.scala
@@ -8,11 +8,11 @@ import firrtl.Utils._
 import firrtl.Mappers._
 import firrtl.traversals.Foreachers._
 import firrtl.WrappedExpression._
-import firrtl.graph.{MutableDiGraph, CyclicException}
+import firrtl.graph.{CyclicException, MutableDiGraph}
 import firrtl.options.Dependency
 
 import scala.collection.mutable
-import scala.util.{Try, Success, Failure}
+import scala.util.{Failure, Success, Try}
 
 /** Replace wires with nodes in a legal, flow-forward order
   *
@@ -23,11 +23,13 @@ import scala.util.{Try, Success, Failure}
 class RemoveWires extends Transform with DependencyAPIMigration {
 
   override def prerequisites = firrtl.stage.Forms.MidForm ++
-    Seq( Dependency(passes.LowerTypes),
-         Dependency(passes.Legalize),
-         Dependency(passes.ResolveKinds),
-         Dependency(transforms.RemoveReset),
-         Dependency[transforms.CheckCombLoops] )
+    Seq(
+      Dependency(passes.LowerTypes),
+      Dependency(passes.Legalize),
+      Dependency(passes.ResolveKinds),
+      Dependency(transforms.RemoveReset),
+      Dependency[transforms.CheckCombLoops]
+    )
 
   override def optionalPrerequisites = Seq(Dependency[checks.CheckResets])
 
@@ -35,7 +37,7 @@ class RemoveWires extends Transform with DependencyAPIMigration {
 
   override def invalidates(a: Transform) = a match {
     case passes.ResolveKinds => true
-    case  _ => false
+    case _                   => false
   }
 
   // Extract all expressions that are references to a Node, Wire, or Reg
@@ -44,7 +46,7 @@ class RemoveWires extends Transform with DependencyAPIMigration {
     val refs = mutable.ArrayBuffer.empty[WRef]
     def rec(e: Expression): Expression = {
       e match {
-        case ref @ WRef(_,_, WireKind | NodeKind | RegKind, _) => refs += ref
+        case ref @ WRef(_, _, WireKind | NodeKind | RegKind, _) => refs += ref
         case nested @ (_: Mux | _: DoPrim | _: ValidIf) => nested.foreach(rec)
         case _ => // Do nothing
       }
@@ -57,7 +59,8 @@ class RemoveWires extends Transform with DependencyAPIMigration {
   // Transform netlist into DefNodes
   private def getOrderedNodes(
     netlist: mutable.LinkedHashMap[WrappedExpression, (Seq[Expression], Info)],
-    regInfo: mutable.Map[WrappedExpression, DefRegister]): Try[Seq[Statement]] = {
+    regInfo: mutable.Map[WrappedExpression, DefRegister]
+  ): Try[Seq[Statement]] = {
     val digraph = new MutableDiGraph[WrappedExpression]
     for ((sink, (exprs, _)) <- netlist) {
       digraph.addVertex(sink)
@@ -106,21 +109,22 @@ class RemoveWires extends Transform with DependencyAPIMigration {
         case reg: DefRegister =>
           val resetDep = reg.reset.tpe match {
             case AsyncResetType => Some(reg.reset)
-            case _ => None
+            case _              => None
           }
           val initDep = Some(reg.init).filter(we(WRef(reg)) != we(_)) // Dependency exists IF reg doesn't init itself
           regInfo(we(WRef(reg))) = reg
           netlist(we(WRef(reg))) = (Seq(reg.clock) ++ resetDep ++ initDep, reg.info)
         case decl: IsDeclaration => // Keep all declarations except for nodes and non-Analog wires
           decls += decl
-        case con @ Connect(cinfo, lhs, rhs) => kind(lhs) match {
-          case WireKind =>
-            // Be sure to pad the rhs since nodes get their type from the rhs
-            val paddedRhs = ConstantPropagation.pad(rhs, lhs.tpe)
-            val dinfo = wireInfo(lhs)
-            netlist(we(lhs)) = (Seq(paddedRhs), MultiInfo(dinfo, cinfo))
-          case _ => otherStmts += con // Other connections just pass through
-        }
+        case con @ Connect(cinfo, lhs, rhs) =>
+          kind(lhs) match {
+            case WireKind =>
+              // Be sure to pad the rhs since nodes get their type from the rhs
+              val paddedRhs = ConstantPropagation.pad(rhs, lhs.tpe)
+              val dinfo = wireInfo(lhs)
+              netlist(we(lhs)) = (Seq(paddedRhs), MultiInfo(dinfo, cinfo))
+            case _ => otherStmts += con // Other connections just pass through
+          }
         case invalid @ IsInvalid(info, expr) =>
           kind(expr) match {
             case WireKind =>
@@ -146,8 +150,10 @@ class RemoveWires extends Transform with DependencyAPIMigration {
           // If we hit a CyclicException, just abort removing wires
           case Failure(c: CyclicException) =>
             val problematicNode = c.node
-            logger.warn(s"Cycle found in module $name, " +
-              s"wires will not be removed which can prevent optimizations! Problem node: $problematicNode")
+            logger.warn(
+              s"Cycle found in module $name, " +
+                s"wires will not be removed which can prevent optimizations! Problem node: $problematicNode"
+            )
             mod
           case Failure(other) => throw other
         }
@@ -155,7 +161,6 @@ class RemoveWires extends Transform with DependencyAPIMigration {
     }
   }
 
-
   def execute(state: CircuitState): CircuitState =
     state.copy(circuit = state.circuit.map(onModule))
 }