diff options
| author | Jack Koenig | 2019-02-14 15:08:35 -0800 |
|---|---|---|
| committer | GitHub | 2019-02-14 15:08:35 -0800 |
| commit | 2272044c6ab46b5148c39c124e66e1a8e9073a24 (patch) | |
| tree | 83ad2141b1a3c54707dd9b33073f9217b0ae16c8 /src/main/scala/firrtl/transforms/RemoveReset.scala | |
| parent | d487b4cb6726e7e8d1a18f894021652594125221 (diff) | |
Asynchronous Reset (#1011)
Fixes #219
* Adds AsyncResetType (similar to ClockType)
* Registers with reset signal of type AsyncResetType are async reset
registers
* Registers with async reset can only be reset to literal values
* Add initialization logic for async reset registers
Diffstat (limited to 'src/main/scala/firrtl/transforms/RemoveReset.scala')
| -rw-r--r-- | src/main/scala/firrtl/transforms/RemoveReset.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/RemoveReset.scala b/src/main/scala/firrtl/transforms/RemoveReset.scala index bfec76a2..0b8b907d 100644 --- a/src/main/scala/firrtl/transforms/RemoveReset.scala +++ b/src/main/scala/firrtl/transforms/RemoveReset.scala @@ -22,7 +22,8 @@ class RemoveReset extends Transform { val resets = mutable.HashMap.empty[String, Reset] def onStmt(stmt: Statement): Statement = { stmt match { - case reg @ DefRegister(_, rname, _, _, reset, init) if reset != Utils.zero => + case reg @ DefRegister(_, rname, _, _, reset, init) + if reset != Utils.zero && reset.tpe != AsyncResetType => // Add register reset to map resets(rname) = Reset(reset, init) reg.copy(reset = Utils.zero, init = WRef(reg)) |