diff options
| author | Schuyler Eldridge | 2020-04-22 19:55:32 -0400 |
|---|---|---|
| committer | GitHub | 2020-04-22 19:55:32 -0400 |
| commit | 65360f886f9b92438d1b6fe609120b34ebb413cf (patch) | |
| tree | 073ebe73d43e652af1f71a08d34cc30a421c4dbb /src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala | |
| parent | 8653fd628f83c1bcb329dd37844ddfdb8f4cf206 (diff) | |
| parent | 184d40095179a9f49dd21e73e2c02b998bac5c00 (diff) | |
Merge pull request #1534 from freechipsproject/deprecate-transform-2
Trait-base Dependency API Migration
Diffstat (limited to 'src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala')
| -rw-r--r-- | src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala index fdb0090e..214692e6 100644 --- a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala +++ b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala @@ -20,9 +20,7 @@ import scala.collection.mutable * @define implicitNamespace @param ns an encolosing [[Namespace]] with which new names must not conflict * @define implicitScope @param scope the enclosing scope of this name. If [[None]], then this is a [[Circuit]] name */ -class RemoveKeywordCollisions(keywords: Set[String]) extends Transform { - val inputForm: CircuitForm = UnknownForm - val outputForm: CircuitForm = UnknownForm +class RemoveKeywordCollisions(keywords: Set[String]) extends Transform with DependencyAPIMigration { private type ModuleType = mutable.HashMap[String, ir.Type] private val inlineDelim = "_" @@ -235,7 +233,7 @@ class RemoveKeywordCollisions(keywords: Set[String]) extends Transform { /** Transform that removes collisions with Verilog keywords */ class VerilogRename extends RemoveKeywordCollisions(v_keywords) with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ + override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[BlackBoxSourceHelper], Dependency[FixAddingNegativeLiterals], Dependency[ReplaceTruncatingArithmetic], @@ -245,8 +243,8 @@ class VerilogRename extends RemoveKeywordCollisions(v_keywords) with PreservesAl Dependency[FlattenRegUpdate], Dependency(passes.VerilogModulusCleanup) ) - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty } |
