Merge pull request #1852 from freechipsproject/format-src-4

Apply Scalafmt Rewriting

1 files changed, 3 insertions, 5 deletions

diff --git a/src/main/scala/firrtl/transforms/LegalizeReductions.scala b/src/main/scala/firrtl/transforms/LegalizeReductions.scala
index 2e60aae7..33a10349 100644
--- a/src/main/scala/firrtl/transforms/LegalizeReductions.scala
+++ b/src/main/scala/firrtl/transforms/LegalizeReductions.scala
@@ -6,17 +6,16 @@ import firrtl.Mappers._
 import firrtl.options.Dependency
 import firrtl.Utils.BoolType
 
-
 object LegalizeAndReductionsTransform {
 
   private def allOnesOfType(tpe: Type): Literal = tpe match {
     case UIntType(width @ IntWidth(x)) => UIntLiteral((BigInt(1) << x.toInt) - 1, width)
-    case SIntType(width) => SIntLiteral(-1, width)
+    case SIntType(width)               => SIntLiteral(-1, width)
 
   }
 
   def onExpr(expr: Expression): Expression = expr.map(onExpr) match {
-    case DoPrim(PrimOps.Andr, Seq(arg), _,_) if bitWidth(arg.tpe) > 64 =>
+    case DoPrim(PrimOps.Andr, Seq(arg), _, _) if bitWidth(arg.tpe) > 64 =>
       DoPrim(PrimOps.Eq, Seq(arg, allOnesOfType(arg.tpe)), Seq(), BoolType)
     case other => other
   }
@@ -35,8 +34,7 @@ class LegalizeAndReductionsTransform extends Transform with DependencyAPIMigrati
 
   override def prerequisites =
     firrtl.stage.Forms.WorkingIR ++
-    Seq( Dependency(passes.CheckTypes),
-         Dependency(passes.CheckWidths))
+      Seq(Dependency(passes.CheckTypes), Dependency(passes.CheckWidths))
 
   override def optionalPrerequisites = Nil