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authorJohn's Brew2020-03-13 02:35:10 +0100
committerGitHub2020-03-12 18:35:10 -0700
commit5c0c0018d812d57270035a9d3bd82e2289acf4ec (patch)
tree3e9c319c0e98566b42540a5f31d043d5d0287c17 /src/main/scala/firrtl/transforms/InlineCasts.scala
parent7e8d21e7f5fe3469eada53e6a6c60e38c134c403 (diff)
Add Support for FPGA Bitstream Preset-registers (#1050)
Introduce Preset Register Specialized Emission - Introduce EmissionOption trait - Introduce PresetAnnotation & PresetRegAnnotation - Enable the collection of Annotations in the Emitter - Introduce collection mechanism for EmissionOptions in the Emitter - Add PropagatePresetAnnotation transform to annotate register for emission and clean-up the useless reset tree (no DCE involved) - Add corresponding tests spec and tester Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'src/main/scala/firrtl/transforms/InlineCasts.scala')
-rw-r--r--src/main/scala/firrtl/transforms/InlineCasts.scala3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/InlineCasts.scala b/src/main/scala/firrtl/transforms/InlineCasts.scala
index 91ba7578..eeafb0e4 100644
--- a/src/main/scala/firrtl/transforms/InlineCasts.scala
+++ b/src/main/scala/firrtl/transforms/InlineCasts.scala
@@ -68,7 +68,8 @@ class InlineCastsTransform extends Transform with PreservesAll[Transform] {
Seq( Dependency[BlackBoxSourceHelper],
Dependency[FixAddingNegativeLiterals],
Dependency[ReplaceTruncatingArithmetic],
- Dependency[InlineBitExtractionsTransform] )
+ Dependency[InlineBitExtractionsTransform],
+ Dependency[PropagatePresetAnnotations] )
override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized