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authorSchuyler Eldridge2020-03-11 14:32:32 -0400
committerGitHub2020-03-11 14:32:32 -0400
commit026c18dd76d4e2121c7f6c582d15e4d5a3ab842b (patch)
tree0537dff3091db3da167c0fffc3388a5966c46204 /src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala
parent646c91e71b8bfb1b0d0f22e81ca113147637ce71 (diff)
parentabf226471249a1cbb8de33d0c4bc8526f9aafa70 (diff)
Merge pull request #1123 from freechipsproject/dependency-api-2
- Use Dependency API for transform scheduling - Add tests that old order/behavior is preserved Or: "Now you're thinking with dependencies."
Diffstat (limited to 'src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala')
-rw-r--r--src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala16
1 files changed, 12 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala b/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala
index 08bf4af4..59d14ab2 100644
--- a/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala
+++ b/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala
@@ -2,10 +2,12 @@
package firrtl.transforms
-import firrtl.{CircuitState, LowForm, Namespace, PrimOps, Transform, Utils, WRef}
+import firrtl.{CircuitState, Namespace, PrimOps, Transform, UnknownForm, Utils, WRef}
import firrtl.ir._
import firrtl.Mappers._
+import firrtl.options.{Dependency, PreservesAll}
import firrtl.PrimOps.{Add, AsSInt, Sub, Tail}
+import firrtl.stage.Forms
import scala.collection.mutable
@@ -105,9 +107,15 @@ object FixAddingNegativeLiterals {
* the literal and thus not all expressions in the add are the same. This is fixed here when we directly
* subtract the literal instead.
*/
-class FixAddingNegativeLiterals extends Transform {
- def inputForm = LowForm
- def outputForm = LowForm
+class FixAddingNegativeLiterals extends Transform with PreservesAll[Transform] {
+ def inputForm = UnknownForm
+ def outputForm = UnknownForm
+
+ override val prerequisites = Forms.LowFormMinimumOptimized :+ Dependency[BlackBoxSourceHelper]
+
+ override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized
+
+ override val dependents = Seq.empty
def execute(state: CircuitState): CircuitState = {
val modulesx = state.circuit.modules.map(FixAddingNegativeLiterals.fixupModule)