Merge pull request #1124 from freechipsproject/gender-to-flow

Gender to Flow

1 files changed, 5 insertions, 5 deletions

diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
index a2f15776..308d68df 100644
--- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
+++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
@@ -108,11 +108,11 @@ class DeadCodeElimination extends Transform with ResolvedAnnotationPaths with Re
         depGraph.addVertex(LogicNode(mod.name, name))
       case mem: DefMemory =>
         // Treat DefMems as a node with outputs depending on the node and node depending on inputs
-        // From perpsective of the module or instance, MALE expressions are inputs, FEMALE are outputs
-        val memRef = WRef(mem.name, MemPortUtils.memType(mem), ExpKind, FEMALE)
-        val exprs = Utils.create_exps(memRef).groupBy(Utils.gender(_))
-        val sources = exprs.getOrElse(MALE, List.empty).flatMap(getDeps(_))
-        val sinks = exprs.getOrElse(FEMALE, List.empty).flatMap(getDeps(_))
+        // From perpsective of the module or instance, SourceFlow expressions are inputs, SinkFlow are outputs
+        val memRef = WRef(mem.name, MemPortUtils.memType(mem), ExpKind, SinkFlow)
+        val exprs = Utils.create_exps(memRef).groupBy(Utils.flow(_))
+        val sources = exprs.getOrElse(SourceFlow, List.empty).flatMap(getDeps(_))
+        val sinks = exprs.getOrElse(SinkFlow, List.empty).flatMap(getDeps(_))
         val memNode = getDeps(memRef) match { case Seq(node) => node }
         depGraph.addVertex(memNode)
         sinks.foreach(sink => depGraph.addPairWithEdge(sink, memNode))