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authorJack Koenig2019-02-14 15:08:35 -0800
committerGitHub2019-02-14 15:08:35 -0800
commit2272044c6ab46b5148c39c124e66e1a8e9073a24 (patch)
tree83ad2141b1a3c54707dd9b33073f9217b0ae16c8 /src/main/scala/firrtl/transforms/ConstantPropagation.scala
parentd487b4cb6726e7e8d1a18f894021652594125221 (diff)
Asynchronous Reset (#1011)
Fixes #219 * Adds AsyncResetType (similar to ClockType) * Registers with reset signal of type AsyncResetType are async reset registers * Registers with async reset can only be reset to literal values * Add initialization logic for async reset registers
Diffstat (limited to 'src/main/scala/firrtl/transforms/ConstantPropagation.scala')
-rw-r--r--src/main/scala/firrtl/transforms/ConstantPropagation.scala6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/ConstantPropagation.scala b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
index 6618312a..fdaa7112 100644
--- a/src/main/scala/firrtl/transforms/ConstantPropagation.scala
+++ b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
@@ -350,6 +350,8 @@ class ConstantPropagation extends Transform with ResolvedAnnotationPaths {
// Keep track of any submodule inputs we drive with a constant
// (can have more than 1 of the same submodule)
val constSubInputs = mutable.HashMap.empty[String, mutable.HashMap[String, Seq[Literal]]]
+ // AsyncReset registers don't have reset turned into a mux so we must be careful
+ val asyncResetRegs = mutable.HashSet.empty[String]
// Copy constant mapping for constant inputs (except ones marked dontTouch!)
nodeMap ++= constInputs.filterNot { case (pname, _) => dontTouches.contains(pname) }
@@ -405,6 +407,8 @@ class ConstantPropagation extends Transform with ResolvedAnnotationPaths {
// Record things that should be propagated
stmtx match {
case x: DefNode if !dontTouches.contains(x.name) => propagateRef(x.name, x.value)
+ case reg: DefRegister if reg.reset.tpe == AsyncResetType =>
+ asyncResetRegs += reg.name
case Connect(_, WRef(wname, wtpe, WireKind, _), expr: Literal) if !dontTouches.contains(wname) =>
val exprx = constPropExpression(nodeMap, instMap, constSubOutputs)(pad(expr, wtpe))
propagateRef(wname, exprx)
@@ -414,7 +418,7 @@ class ConstantPropagation extends Transform with ResolvedAnnotationPaths {
constOutputs(pname) = paddedLit
// Const prop registers that are driven by a mux tree containing only instances of one constant or self-assigns
// This requires that reset has been made explicit
- case Connect(_, lref @ WRef(lname, ltpe, RegKind, _), rhs) if !dontTouches.contains(lname) =>
+ case Connect(_, lref @ WRef(lname, ltpe, RegKind, _), rhs) if !dontTouches(lname) && !asyncResetRegs(lname) =>
/** Checks if an RHS expression e of a register assignment is convertible to a constant assignment.
* Here, this means that e must be 1) a literal, 2) a self-connect, or 3) a mux tree of cases (1) and (2).
* In case (3), it also recursively checks that the two mux cases are convertible to constants and