Merge pull request #1123 from freechipsproject/dependency-api-2

- Use Dependency API for transform scheduling
- Add tests that old order/behavior is preserved

Or: "Now you're thinking with dependencies."

1 files changed, 16 insertions, 1 deletions

diff --git a/src/main/scala/firrtl/transforms/CombineCats.scala b/src/main/scala/firrtl/transforms/CombineCats.scala
index ac8fc5fb..8f5972e1 100644
--- a/src/main/scala/firrtl/transforms/CombineCats.scala
+++ b/src/main/scala/firrtl/transforms/CombineCats.scala
@@ -7,6 +7,8 @@ import firrtl.Mappers._
 import firrtl.PrimOps._
 import firrtl.WrappedExpression._
 import firrtl.annotations.NoTargetAnnotation
+import firrtl.options.PreservesAll
+import firrtl.options.Dependency
 
 import scala.collection.mutable
 
@@ -51,9 +53,22 @@ object CombineCats {
   * Use [[MaxCatLenAnnotation]] to limit the number of elements that can be concatenated.
   * The default maximum number of elements is 10.
   */
-class CombineCats extends Transform {
+class CombineCats extends Transform with PreservesAll[Transform] {
   def inputForm: LowForm.type = LowForm
   def outputForm: LowForm.type = LowForm
+
+  override val prerequisites = firrtl.stage.Forms.LowForm ++
+    Seq( Dependency(passes.RemoveValidIf),
+         Dependency[firrtl.transforms.ConstantPropagation],
+         Dependency(firrtl.passes.memlib.VerilogMemDelays),
+         Dependency(firrtl.passes.SplitExpressions) )
+
+  override val optionalPrerequisites = Seq.empty
+
+  override val dependents = Seq(
+    Dependency[SystemVerilogEmitter],
+    Dependency[VerilogEmitter] )
+
   val defaultMaxCatLen = 10
 
   def execute(state: CircuitState): CircuitState = {