diff options
| author | Jack | 2016-05-10 01:38:20 -0700 |
|---|---|---|
| committer | Jack Koenig | 2016-06-10 16:43:06 -0700 |
| commit | f162263c05643c0851c5200fff2fc356f97843cd (patch) | |
| tree | e5d49ea105d189320439aa2f1b0b9ab6ec98b603 /src/main/scala/firrtl/passes | |
| parent | 58d9f1d50c07d999776c76259fadbdfd52c564fc (diff) | |
API Cleanup - AST
trait AST -> abstract class FirrtlNode
Move all IR to new package ir
Add import of firrtl.ir._
Diffstat (limited to 'src/main/scala/firrtl/passes')
| -rw-r--r-- | src/main/scala/firrtl/passes/CheckInitialization.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/Checks.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/ConstProp.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/DeadCodeElimination.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/ExpandWhens.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/Inline.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/LowerTypes.scala | 11 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/PadWidths.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/Passes.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveValidIf.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/SplitExpressions.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/Uniquify.scala | 3 |
13 files changed, 19 insertions, 6 deletions
diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala index d364f0dc..6d69b792 100644 --- a/src/main/scala/firrtl/passes/CheckInitialization.scala +++ b/src/main/scala/firrtl/passes/CheckInitialization.scala @@ -28,6 +28,7 @@ MODIFICATIONS. package firrtl.passes import firrtl._ +import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala index 5a4f613c..ebdd2469 100644 --- a/src/main/scala/firrtl/passes/Checks.scala +++ b/src/main/scala/firrtl/passes/Checks.scala @@ -34,6 +34,7 @@ import scala.collection.mutable.HashMap import scala.collection.mutable.ArrayBuffer import firrtl._ +import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ import firrtl.Serialize._ diff --git a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala index f58572b1..7d4c96b2 100644 --- a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala +++ b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala @@ -28,6 +28,7 @@ MODIFICATIONS. package firrtl.passes import firrtl._ +import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala index f8fd5654..618a96c0 100644 --- a/src/main/scala/firrtl/passes/ConstProp.scala +++ b/src/main/scala/firrtl/passes/ConstProp.scala @@ -28,6 +28,7 @@ MODIFICATIONS. package firrtl.passes import firrtl._ +import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ import firrtl.PrimOps._ diff --git a/src/main/scala/firrtl/passes/DeadCodeElimination.scala b/src/main/scala/firrtl/passes/DeadCodeElimination.scala index 8482fe1d..80ba0e98 100644 --- a/src/main/scala/firrtl/passes/DeadCodeElimination.scala +++ b/src/main/scala/firrtl/passes/DeadCodeElimination.scala @@ -28,6 +28,7 @@ MODIFICATIONS. package firrtl.passes import firrtl._ +import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala index e20ed793..b6e090f4 100644 --- a/src/main/scala/firrtl/passes/ExpandWhens.scala +++ b/src/main/scala/firrtl/passes/ExpandWhens.scala @@ -28,6 +28,7 @@ MODIFICATIONS. package firrtl.passes import firrtl._ +import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ import firrtl.PrimOps._ diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala index d120426b..786de0eb 100644 --- a/src/main/scala/firrtl/passes/Inline.scala +++ b/src/main/scala/firrtl/passes/Inline.scala @@ -6,6 +6,7 @@ import scala.collection.mutable import firrtl.Mappers.{ExpMap,StmtMap} import firrtl.Utils.WithAs +import firrtl.ir._ // Tags an annotation to be consumed by this pass diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala index d905fc34..b86b0651 100644 --- a/src/main/scala/firrtl/passes/LowerTypes.scala +++ b/src/main/scala/firrtl/passes/LowerTypes.scala @@ -30,16 +30,17 @@ package firrtl.passes import com.typesafe.scalalogging.LazyLogging import firrtl._ +import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ // Datastructures import scala.collection.mutable.HashMap -/** Removes all aggregate types from a [[Circuit]] +/** Removes all aggregate types from a [[firrtl.ir.Circuit]] * - * @note Assumes [[firrtl.SubAccess]]es have been removed - * @note Assumes [[firrtl.Connect]]s and [[firrtl.IsInvalid]]s only operate on [[firrtl.Expression]]s of ground type + * @note Assumes [[firrtl.ir.SubAccess]]es have been removed + * @note Assumes [[firrtl.ir.Connect]]s and [[firrtl.ir.IsInvalid]]s only operate on [[firrtl.ir.Expression]]s of ground type * @example * {{{ * wire foo : { a : UInt<32>, b : UInt<16> } @@ -54,8 +55,8 @@ object LowerTypes extends Pass { /** Delimiter used in lowering names */ val delim = "_" - /** Expands a chain of referential [[firrtl.Expression]]s into the equivalent lowered name - * @param e [[firrtl.Expression]] made up of _only_ [[firrtl.WRef]], [[firrtl.WSubField]], and [[firrtl.WSubIndex]] + /** Expands a chain of referential [[firrtl.ir.Expression]]s into the equivalent lowered name + * @param e [[firrtl.ir.Expression]] made up of _only_ [[firrtl.WRef]], [[firrtl.WSubField]], and [[firrtl.WSubIndex]] * @return Lowered name of e */ def loweredName(e: Expression): String = e match { diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala index 0d269a98..0cabc293 100644 --- a/src/main/scala/firrtl/passes/PadWidths.scala +++ b/src/main/scala/firrtl/passes/PadWidths.scala @@ -4,6 +4,7 @@ package passes import firrtl.Mappers.{ExpMap, StmtMap} import firrtl.Utils.{tpe, long_BANG} import firrtl.PrimOps._ +import firrtl.ir._ // Makes all implicit width extensions and truncations explicit object PadWidths extends Pass { diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala index 739d0c2f..6b88c514 100644 --- a/src/main/scala/firrtl/passes/Passes.scala +++ b/src/main/scala/firrtl/passes/Passes.scala @@ -36,6 +36,7 @@ import scala.collection.mutable.HashMap import scala.collection.mutable.ArrayBuffer import firrtl._ +import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ import firrtl.Serialize._ diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala index 486e9ff8..a534cc50 100644 --- a/src/main/scala/firrtl/passes/RemoveValidIf.scala +++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala @@ -1,6 +1,7 @@ package firrtl package passes import firrtl.Mappers.{ExpMap, StmtMap} +import firrtl.ir._ // Removes ValidIf as an optimization object RemoveValidIf extends Pass { diff --git a/src/main/scala/firrtl/passes/SplitExpressions.scala b/src/main/scala/firrtl/passes/SplitExpressions.scala index 61f01e01..973e1be9 100644 --- a/src/main/scala/firrtl/passes/SplitExpressions.scala +++ b/src/main/scala/firrtl/passes/SplitExpressions.scala @@ -3,6 +3,7 @@ package passes import firrtl.Mappers.{ExpMap, StmtMap} import firrtl.Utils.{tpe, kind, gender, info} +import firrtl.ir._ import scala.collection.mutable diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala index 3ad0c3dc..aa2c1d5d 100644 --- a/src/main/scala/firrtl/passes/Uniquify.scala +++ b/src/main/scala/firrtl/passes/Uniquify.scala @@ -31,12 +31,13 @@ import com.typesafe.scalalogging.LazyLogging import scala.annotation.tailrec import firrtl._ +import firrtl.ir._ import firrtl.Utils._ import firrtl.Mappers._ /** Resolve name collisions that would occur in [[LowerTypes]] * - * @note Must be run after [[InferTypes]] because [[DefNode]]s need type + * @note Must be run after [[InferTypes]] because [[ir.DefNode]]s need type * @example * {{{ * wire a = { b, c }[2] |
