Replacematcherror - catch exceptions and convert to internal error. (#424)

* Catch exceptions and convert to internal error.
We need to update the displayed message to incorporate a line number and text to be used for the issue.

* Cleanup exception handling/throwing.
Re-throw expected (or uncorrectable exceptions).
Provide Utils.getThrowable() to get the first (eldest) or last throwable in the chain.
Update tests to conform to FreeSpec protocol.

* Minor cleanup
Admit we've updated some deprecated ScalaTest methods.

11 files changed, 17 insertions, 16 deletions

diff --git a/src/main/scala/firrtl/passes/CheckWidths.scala b/src/main/scala/firrtl/passes/CheckWidths.scala
index 8f6ab18f..55391d99 100644
--- a/src/main/scala/firrtl/passes/CheckWidths.scala
+++ b/src/main/scala/firrtl/passes/CheckWidths.scala
@@ -50,7 +50,7 @@ object CheckWidths extends Pass {
     def hasWidth(tpe: Type): Boolean = tpe match {
       case GroundType(IntWidth(w)) => true
       case GroundType(_) => false
-      case _ => println(tpe); throwInternalError
+      case _ => throwInternalError(Some(s"hasWidth - $tpe"))
     }
 
     def check_width_t(info: Info, mname: String)(t: Type): Type =
diff --git a/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala b/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala
index 05604bd8..b52dacb7 100644
--- a/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala
+++ b/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala
@@ -7,7 +7,7 @@ import firrtl.PrimOps._
 import firrtl.ir._
 import firrtl._
 import firrtl.Mappers._
-import firrtl.Utils.{sub_type, module_type, field_type, max, error}
+import firrtl.Utils.{sub_type, module_type, field_type, max, error, throwInternalError}
 
 /** Replaces FixedType with SIntType, and correctly aligns all binary points
   */
@@ -19,7 +19,7 @@ object ConvertFixedToSInt extends Pass {
       } else if (point - p < 0) {
         DoPrim(Shr, Seq(e), Seq(p - point), UnknownType)
       } else e
-    case FixedType(w, p) => error("Shouldn't be here")
+    case FixedType(w, p) => throwInternalError(Some(s"alignArg: shouldn't be here - $e"))
     case _ => e
   }
   def calcPoint(es: Seq[Expression]): BigInt =
@@ -29,7 +29,7 @@ object ConvertFixedToSInt extends Pass {
     }).reduce(max(_, _))
   def toSIntType(t: Type): Type = t match {
     case FixedType(IntWidth(w), IntWidth(p)) => SIntType(IntWidth(w))
-    case FixedType(w, p) => error("Shouldn't be here")
+    case FixedType(w, p) => throwInternalError(Some(s"toSIntType: shouldn't be here - $t"))
     case _ => t map toSIntType
   }
   def run(c: Circuit): Circuit = {
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index 959e824a..519a1e1a 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -169,7 +169,7 @@ object ExpandWhens extends Pass {
         }
         Block(Seq(conseqStmt, altStmt) ++ memos)
       case block: Block => block map expandWhens(netlist, defaults, p)
-      case _ => throwInternalError
+      case _ => throwInternalError()
     }
     val netlist = new Netlist
     // Add ports to netlist
diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala
index 11b819ce..aacd3656 100644
--- a/src/main/scala/firrtl/passes/InferWidths.scala
+++ b/src/main/scala/firrtl/passes/InferWidths.scala
@@ -333,7 +333,7 @@ object InferWidths extends Pass {
         case wx: MinusWidth => map2(solve(wx.arg1), solve(wx.arg2), {_ - _})
         case wx: ExpWidth => map2(Some(BigInt(2)), solve(wx.arg1), pow_minus_one)
         case wx: IntWidth => Some(wx.width)
-        case wx => println(wx); error("Shouldn't be here"); None;
+        case wx => throwInternalError(Some(s"solve: shouldn't be here - %$wx")); None;
       }
 
       solve(w) match {
diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala
index 37b92a9e..9b19b221 100644
--- a/src/main/scala/firrtl/passes/RemoveAccesses.scala
+++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala
@@ -95,7 +95,7 @@ object RemoveAccesses extends Pass {
           case (_:WSubAccess| _: WSubField| _: WSubIndex| _: WRef) if hasAccess(e) =>
             val rs = getLocations(e)
             rs find (x => x.guard != one) match {
-              case None => error("Shouldn't be here")
+              case None => throwInternalError(Some(s"removeMale: shouldn't be here - $e"))
               case Some(_) =>
                 val (wire, temp) = create_temp(e)
                 val temps = create_exps(temp)
diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala
index 68d16c30..7d714be7 100644
--- a/src/main/scala/firrtl/passes/RemoveValidIf.scala
+++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala
@@ -24,7 +24,7 @@ object RemoveValidIf extends Pass {
     case _: UIntType => UIntZero
     case _: SIntType => SIntZero
     case ClockType => ClockZero
-    case other => throwInternalError
+    case other => throwInternalError()
   }
 
   // Recursive. Replaces IsInvalid with connecting zero
diff --git a/src/main/scala/firrtl/passes/Resolves.scala b/src/main/scala/firrtl/passes/Resolves.scala
index c8ba43bf..b601c81e 100644
--- a/src/main/scala/firrtl/passes/Resolves.scala
+++ b/src/main/scala/firrtl/passes/Resolves.scala
@@ -5,6 +5,7 @@ package firrtl.passes
 import firrtl._
 import firrtl.ir._
 import firrtl.Mappers._
+import Utils.throwInternalError
 
 object ResolveKinds extends Pass {
   type KindMap = collection.mutable.LinkedHashMap[String, Kind]
@@ -84,19 +85,19 @@ object CInferMDir extends Pass {
       mports get e.name match {
         case None =>
         case Some(p) => mports(e.name) = (p, dir) match {
-          case (MInfer, MInfer) => Utils.error("Shouldn't be here")
+          case (MInfer, MInfer) => throwInternalError(Some(s"infer_mdir_e: shouldn't be here - $p, $dir"))
           case (MInfer, MWrite) => MWrite
           case (MInfer, MRead) => MRead
           case (MInfer, MReadWrite) => MReadWrite
-          case (MWrite, MInfer) => Utils.error("Shouldn't be here")
+          case (MWrite, MInfer) => throwInternalError(Some(s"infer_mdir_e: shouldn't be here - $p, $dir"))
           case (MWrite, MWrite) => MWrite
           case (MWrite, MRead) => MReadWrite
           case (MWrite, MReadWrite) => MReadWrite
-          case (MRead, MInfer) => Utils.error("Shouldn't be here")
+          case (MRead, MInfer) => throwInternalError(Some(s"infer_mdir_e: shouldn't be here - $p, $dir"))
           case (MRead, MWrite) => MReadWrite
           case (MRead, MRead) => MRead
           case (MRead, MReadWrite) => MReadWrite
-          case (MReadWrite, MInfer) => Utils.error("Shouldn't be here")
+          case (MReadWrite, MInfer) => throwInternalError(Some(s"infer_mdir_e: shouldn't be here - $p, $dir"))
           case (MReadWrite, MWrite) => MReadWrite
           case (MReadWrite, MRead) => MReadWrite
           case (MReadWrite, MReadWrite) => MReadWrite
diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala
index 54b94939..661dbf4e 100644
--- a/src/main/scala/firrtl/passes/Uniquify.scala
+++ b/src/main/scala/firrtl/passes/Uniquify.scala
@@ -109,7 +109,7 @@ object Uniquify extends Transform {
     }
     recUniquifyNames(t, namespace) match {
       case tx: BundleType => tx
-      case tx => error("Shouldn't be here")
+      case tx => throwInternalError(Some(s"uniquifyNames: shouldn't be here - $tx"))
     }
   }
 
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockList.scala b/src/main/scala/firrtl/passes/clocklist/ClockList.scala
index 073eb050..be4d99fc 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockList.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockList.scala
@@ -44,7 +44,7 @@ class ClockList(top: String, writer: Writer) extends Pass {
     val modulesToInline = (c.modules.collect { case Module(_, n, _, _) if n != top => ModuleName(n, CircuitName(c.main)) }).toSet
     val inlineTransform = new InlineInstances
     val inlinedCircuit = inlineTransform.run(onlyClockCircuit, modulesToInline, Set(), None).circuit
-    val topModule = inlinedCircuit.modules.find(_.name == top).getOrElse(throwInternalError)
+    val topModule = inlinedCircuit.modules.find(_.name == top).getOrElse(throwInternalError(Some("no top module")))
 
     // Build a hashmap of connections to use for getOrigins
     val connects = getConnects(topModule)
diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
index b18ed289..bf0612ac 100644
--- a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
+++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
@@ -224,7 +224,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Transform {
     val pins = getMyAnnotations(state) match {
       case Nil => Nil
       case Seq(PinAnnotation(CircuitName(c), pins)) => pins
-      case _ => throwInternalError
+      case _ => throwInternalError(Some(s"execute: getMyAnnotations - ${getMyAnnotations(state)}"))
     }
     val annos = (pins.foldLeft(Seq[Annotation]()) { (seq, pin) =>
       seq ++ memMods.collect { 
diff --git a/src/main/scala/firrtl/passes/memlib/YamlUtils.scala b/src/main/scala/firrtl/passes/memlib/YamlUtils.scala
index 4cc28e42..3e0c6a44 100644
--- a/src/main/scala/firrtl/passes/memlib/YamlUtils.scala
+++ b/src/main/scala/firrtl/passes/memlib/YamlUtils.scala
@@ -31,7 +31,7 @@ class YamlFileReader(file: String) {
         catch { case e: Exception => None }
       )
     }
-    else error("Yaml file doesn't exist!")
+    else sys.error("Yaml file doesn't exist!")
   }
 }