Spec features added: AnalogType and Attach (#295)

* Spec features added: AnalogType and Attach

AnalogType(width: Width):
  - Concrete syntax:
      wire x: AnalogType<10>
  - New groundtype, very restricted in use cases.
  - Can only declare ports and wires with Analog type
  - Analog types are never equivalent, thus if x and y have Analog
    types: x <= y is never legal.

Attach(info: Info, source: Expression, exprs: Seq[Expression]):
  - Concrete syntax:
      attach x to (y, z)
  - New statement
  - Source can be any groundtyped expression (UInt, SInt, Analog, Clock)
  - Exprs must have an Analog type reference an instance port
  - Source and exprs must have identical widths

Included WDefInstanceConnector to enable emission of Verilog inout
Should be mostly feature complete.
Need to update spec if PR gets accepted.

* Fixed bug where invalidated ports aren't handled

* Bugfix for VerilogPrep

Intermediate wires for invalidated instance ports were not invalidated

* Bugfix: calling create_exp with name/tpe

Returns unknown gender, which was passing through
Caused temporary wire to not be declared
Because Verilog is dumb, undeclared wires are assumed to be 1bit signals

* Addressed donggyukim's style comments

* Reworked pass to only allow analog types in attach

Restrict source to be only wire or port kind
Much simpler implementation, almost identical functionality
Clearer semantics (i think?)

* Fixup bugs from pulling in new changes from master

* comments for type eqs and small style fixes

6 files changed, 112 insertions, 23 deletions

diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 03ea106c..e3c85edb 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -265,6 +265,8 @@ object CheckTypes extends Pass {
     s"$info: [module $mname]  Primop $op requires all arguments to be UInt type.")
   class OpNotAllSameType(info: Info, mname: String, op: String) extends PassException(
     s"$info: [module $mname]  Primop $op requires all operands to have the same type.")
+  class OpNotAnalog(info: Info, mname: String, exp: String) extends PassException(
+    s"$info: [module $mname]  Attach requires all arguments to be Analog type: $exp.")
   class NodePassiveType(info: Info, mname: String) extends PassException(
     s"$info: [module $mname]  Node must be a passive type.")
   class MuxSameType(info: Info, mname: String) extends PassException(
@@ -277,6 +279,12 @@ object CheckTypes extends Pass {
     s"$info: [module $mname]  Must validif a passive type.")
   class ValidIfCondUInt(info: Info, mname: String) extends PassException(
     s"$info: [module $mname]  A validif condition must be of type UInt.")
+  class IllegalAnalogDeclaration(info: Info, mname: String, decName: String) extends PassException(
+    s"$info: [module $mname]  Cannot declare a reg, node, or memory with an Analog type: $decName.")
+  class IllegalAttachSource(info: Info, mname: String, sourceName: String) extends PassException(
+    s"$info: [module $mname]  Attach source must be a wire or port with an analog type: $sourceName.")
+  class IllegalAttachExp(info: Info, mname: String, expName: String) extends PassException(
+    s"$info: [module $mname]  Attach expression must be an instance: $expName.")
 
   //;---------------- Helper Functions --------------
   def ut: UIntType = UIntType(UnknownWidth)
@@ -291,13 +299,12 @@ object CheckTypes extends Pass {
       case (t: BundleType) => t.fields forall (x => x.flip == Default && passive(x.tpe))
       case (t) => true
     }
-
     def check_types_primop(info: Info, mname: String, e: DoPrim) {
       def all_same_type (ls:Seq[Expression]) {
         if (ls exists (x => wt(ls.head.tpe) != wt(e.tpe)))
           errors append new OpNotAllSameType(info, mname, e.op.serialize)
       }
-      def all_ground (ls: Seq[Expression]) {
+      def allInt(ls: Seq[Expression]) {
         if (ls exists (x => x.tpe match {
           case _: UIntType | _: SIntType => false
           case _ => true
@@ -315,12 +322,11 @@ object CheckTypes extends Pass {
           case _ => true
         }) errors append new OpNotUInt(info, mname, e.op.serialize, x.serialize)
       }
-
       e.op match {
         case AsUInt | AsSInt | AsClock =>
-        case Dshl => is_uint(e.args(1)); all_ground(e.args)
-        case Dshr => is_uint(e.args(1)); all_ground(e.args)
-        case _ => all_ground(e.args)
+        case Dshl => is_uint(e.args(1)); allInt(e.args)
+        case Dshr => is_uint(e.args(1)); allInt(e.args)
+        case _ => allInt(e.args)
       }
     }
 
@@ -377,6 +383,7 @@ object CheckTypes extends Pass {
         case (ClockType, ClockType) => flip1 == flip2
         case (_: UIntType, _: UIntType) => flip1 == flip2
         case (_: SIntType, _: SIntType) => flip1 == flip2
+        case (_: AnalogType, _: AnalogType) => false
         case (t1: BundleType, t2: BundleType) =>
           val t1_fields = (t1.fields foldLeft Map[String, (Type, Orientation)]())(
             (map, f1) => map + (f1.name -> (f1.tpe, f1.flip)))
@@ -397,14 +404,35 @@ object CheckTypes extends Pass {
       s match {
         case (s: Connect) if wt(s.loc.tpe) != wt(s.expr.tpe) =>
           errors append new InvalidConnect(info, mname, s.loc.serialize, s.expr.serialize)
-        case (s:PartialConnect) if !bulk_equals(s.loc.tpe, s.expr.tpe, Default, Default) =>
+        case (s: PartialConnect) if !bulk_equals(s.loc.tpe, s.expr.tpe, Default, Default) =>
           errors append new InvalidConnect(info, mname, s.loc.serialize, s.expr.serialize)
-        case (s: DefRegister) if wt(s.tpe) != wt(s.init.tpe) =>
-          errors append new InvalidRegInit(info, mname)
+        case (s: DefRegister) => s.tpe match {
+          case AnalogType(w) => errors append new IllegalAnalogDeclaration(info, mname, s.name)
+          case t if (wt(s.tpe) != wt(s.init.tpe)) => errors append new InvalidRegInit(info, mname)
+          case t =>
+        }
         case (s: Conditionally) if wt(s.pred.tpe) != wt(ut) =>
           errors append new PredNotUInt(info, mname)
-        case (s: DefNode) if !passive(s.value.tpe) =>
-          errors append new NodePassiveType(info, mname)
+        case (s: DefNode) => s.value.tpe match {
+          case AnalogType(w) => errors append new IllegalAnalogDeclaration(info, mname, s.name)
+          case t if !passive(s.value.tpe) => errors append new NodePassiveType(info, mname)
+          case t =>
+        }
+        case (s: Attach) => 
+          (s.source.tpe, kind(s.source)) match {
+            case (AnalogType(w), PortKind | WireKind)  =>
+            case _ => errors append new IllegalAttachSource(info, mname, s.source.serialize)
+          }
+          (s.exprs foreach) { e =>
+            e.tpe match {
+              case _: AnalogType =>
+              case _ => errors append new OpNotAnalog(info, mname, e.serialize)
+            }
+            kind(e) match {
+              case InstanceKind =>
+              case _ =>  errors append new IllegalAttachExp(info, mname, e.serialize)
+            }
+          }
         case (s: Stop) =>
           if (wt(s.clk.tpe) != wt(ClockType)) errors append new ReqClk(info, mname)
           if (wt(s.en.tpe) != wt(ut)) errors append new EnNotUInt(info, mname)
@@ -413,6 +441,10 @@ object CheckTypes extends Pass {
             errors append new PrintfArgNotGround(info, mname)
           if (wt(s.clk.tpe) != wt(ClockType)) errors append new ReqClk(info, mname)
           if (wt(s.en.tpe) != wt(ut)) errors append new EnNotUInt(info, mname)
+        case (s: DefMemory) => s.dataType match {
+          case AnalogType(w) => errors append new IllegalAnalogDeclaration(info, mname, s.name)
+          case t =>
+        }
         case _ =>
       }
       s map check_types_e(info, mname) map check_types_s(info, mname)
@@ -541,6 +573,8 @@ object CheckWidths extends Pass {
     s"$info: [module $mname] Parameter $n in head operator is larger than input width $width.")
   class TailWidthException(info: Info, mname: String, n: BigInt, width: BigInt) extends PassException(
     s"$info: [module $mname] Parameter $n in tail operator is larger than input width $width.")
+  class AttachWidthsNotEqual(info: Info, mname: String, eName: String, source: String) extends PassException(
+    s"$info: [module $mname] Attach source $source and expression $eName must have identical widths.")
 
   def run(c: Circuit): Circuit = {
     val errors = new Errors()
@@ -581,7 +615,15 @@ object CheckWidths extends Pass {
 
     def check_width_s(minfo: Info, mname: String)(s: Statement): Statement = {
       val info = get_info(s) match { case NoInfo => minfo case x => x }
-      s map check_width_e(info, mname) map check_width_s(info, mname)
+      s map check_width_e(info, mname) map check_width_s(info, mname) match {
+        case Attach(info, source, exprs) => 
+          exprs foreach ( e =>
+            if (bitWidth(e.tpe) != bitWidth(source.tpe))
+              errors append new AttachWidthsNotEqual(info, mname, e.serialize, source.serialize)
+          )
+          s
+        case _ => s
+      }
     }
 
     def check_width_p(minfo: Info, mname: String)(p: Port): Port = {
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index cd85c18a..f063e6eb 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -48,6 +48,7 @@ object ExpandWhens extends Pass {
   type NodeMap = collection.mutable.HashMap[MemoizedHash[Expression], String]
   type Netlist = collection.mutable.LinkedHashMap[WrappedExpression, Expression]
   type Simlist = collection.mutable.ArrayBuffer[Statement]
+  type Attachlist = collection.mutable.ArrayBuffer[Statement]
   type Defaults = Seq[collection.mutable.Map[WrappedExpression, Expression]]
 
   // ========== Expand When Utilz ==========
@@ -55,9 +56,12 @@ object ExpandWhens extends Pass {
     def getGender(t: Type, i: Int, g: Gender): Gender = times(g, get_flip(t, i, Default))
     val exps = create_exps(WRef(n, t, ExpKind, g))
     (exps.zipWithIndex foldLeft Seq[Expression]()){
-      case (expsx, (exp, j)) => getGender(t, j, g) match {
-        case (BIGENDER | FEMALE) => expsx :+ exp
-        case _ => expsx
+      case (expsx, (exp, j)) => exp.tpe match {
+        case AnalogType(w) => expsx
+        case _ => getGender(t, j, g) match {
+          case (BIGENDER | FEMALE) => expsx :+ exp
+          case _ => expsx
+        }
       }
     }
   }
@@ -108,6 +112,7 @@ object ExpandWhens extends Pass {
         case c: IsInvalid =>
           netlist(c.expr) = WInvalid
           EmptyStmt
+        case c: Attach => c
         case s: Conditionally =>
           val conseqNetlist = new Netlist
           val altNetlist = new Netlist
diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala
index 1a8cc343..bf1f53b4 100644
--- a/src/main/scala/firrtl/passes/InferWidths.scala
+++ b/src/main/scala/firrtl/passes/InferWidths.scala
@@ -253,6 +253,8 @@ object InferWidths extends Pass {
            WGeq(getWidth(s.pred), IntWidth(1)),
            WGeq(IntWidth(1), getWidth(s.pred))
         )
+        case (s: Attach) =>
+          v += WGeq(getWidth(s.source), MaxWidth(s.exprs map (e => getWidth(e.tpe))))
         case _ =>
       }
       s map get_constraints_e map get_constraints_s
@@ -260,13 +262,13 @@ object InferWidths extends Pass {
 
     c.modules foreach (_ map get_constraints_s)
 
-    //println-debug("======== ALL CONSTRAINTS ========")
-    //for x in v do : println-debug(x)
-    //println-debug("=================================")
+    //println("======== ALL CONSTRAINTS ========")
+    //for(x <- v) println(x)
+    //println("=================================")
     val h = solve_constraints(v)
-    //println-debug("======== SOLVED CONSTRAINTS ========")
-    //for x in h do : println-debug(x)
-    //println-debug("====================================")
+    //println("======== SOLVED CONSTRAINTS ========")
+    //for(x <- h) println(x)
+    //println("====================================")
 
     def evaluate(w: Width): Width = {
       def map2(a: Option[BigInt], b: Option[BigInt], f: (BigInt,BigInt) => BigInt): Option[BigInt] =
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index 7e2623c4..92673433 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -140,8 +140,7 @@ object createMask {
   def apply(dt: Type): Type = dt match {
     case t: VectorType => VectorType(apply(t.tpe), t.size)
     case t: BundleType => BundleType(t.fields map (f => f copy (tpe=apply(f.tpe))))
-    case t: UIntType => BoolType
-    case t: SIntType => BoolType
+    case t: GroundType => BoolType
   }
 }
 
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index a182b2af..dc0eb2a0 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -308,3 +308,43 @@ object VerilogRename extends Pass {
   def run(c: Circuit): Circuit =
     c copy (modules = (c.modules map (_ map verilogRenameP map verilogRenameS)))
 }
+
+
+object VerilogPrep extends Pass {
+  def name = "Verilog Prep"
+  type InstAttaches = collection.mutable.HashMap[String, Expression]
+  def run(c: Circuit): Circuit = {
+    def buildS(attaches: InstAttaches)(s: Statement): Statement = s match {
+      case Attach(_, source, exps) => 
+        exps foreach { e => attaches(e.serialize) = source }
+        s
+      case _ => s map buildS(attaches)
+    }
+    def lowerE(e: Expression): Expression = e match {
+      case _: WRef|_: WSubField if (kind(e) == InstanceKind) => 
+        WRef(LowerTypes.loweredName(e), e.tpe, kind(e), gender(e))
+      case _ => e map lowerE
+    }
+    def lowerS(attaches: InstAttaches)(s: Statement): Statement = s match {
+      case WDefInstance(info, name, module, tpe) =>
+        val exps = create_exps(WRef(name, tpe, ExpKind, MALE))
+        val wcon = WDefInstanceConnector(info, name, module, tpe, exps.map( e => e.tpe match {
+          case AnalogType(w) => attaches(e.serialize)
+          case _ => WRef(LowerTypes.loweredName(e), e.tpe, WireKind, MALE)
+        }))
+        val wires = exps.map ( e => e.tpe match {
+          case AnalogType(w) => EmptyStmt
+          case _ => DefWire(info, LowerTypes.loweredName(e), e.tpe)
+        })
+        Block(Seq(wcon) ++ wires)
+      case Attach(info, source, exps) => EmptyStmt
+      case _ => s map lowerS(attaches) map lowerE
+    }
+    def prepModule(m: DefModule): DefModule = {
+      val attaches = new InstAttaches
+      m map buildS(attaches)
+      m map lowerS(attaches)
+    }
+    c copy (modules = (c.modules map prepModule))
+  }
+}
diff --git a/src/main/scala/firrtl/passes/Resolves.scala b/src/main/scala/firrtl/passes/Resolves.scala
index 616e30f3..49df9ba6 100644
--- a/src/main/scala/firrtl/passes/Resolves.scala
+++ b/src/main/scala/firrtl/passes/Resolves.scala
@@ -87,6 +87,7 @@ object ResolveGenders extends Pass {
   }
         
   def resolve_s(s: Statement): Statement = s match {
+    //TODO(azidar): pretty sure don't need to do anything for Attach, but not positive...
     case IsInvalid(info, expr) =>
       IsInvalid(info, resolve_e(FEMALE)(expr))
     case Connect(info, loc, expr) =>