Addresses #459. Rewords transform annotations API.

Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.

6 files changed, 14 insertions, 14 deletions

diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index 93ec6cea..f4556733 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -49,7 +49,7 @@ class InlineInstances extends Transform {
        case Nil => CircuitState(state.circuit, state.form)
        case myAnnotations =>
          val (modNames, instNames) = collectAnns(state.circuit, myAnnotations)
-         run(state.circuit, modNames, instNames)
+         run(state.circuit, modNames, instNames, state.annotations)
      }
    }
 
@@ -93,7 +93,7 @@ class InlineInstances extends Transform {
    }
 
 
-  def run(c: Circuit, modsToInline: Set[ModuleName], instsToInline: Set[ComponentName]): CircuitState = {
+  def run(c: Circuit, modsToInline: Set[ModuleName], instsToInline: Set[ComponentName], annos: Option[AnnotationMap]): CircuitState = {
     def getInstancesOf(c: Circuit, modules: Set[String]): Set[String] =
       c.modules.foldLeft(Set[String]()) { (set, d) =>
         d match {
@@ -146,6 +146,6 @@ class InlineInstances extends Transform {
       case m => 
         Some(m map onStmt("", m.name))
     })
-    CircuitState(flatCircuit, LowForm, None, None)
+    CircuitState(flatCircuit, LowForm, annos, None)
   }
 }
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockList.scala b/src/main/scala/firrtl/passes/clocklist/ClockList.scala
index 231afbdd..66139c49 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockList.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockList.scala
@@ -44,7 +44,7 @@ class ClockList(top: String, writer: Writer) extends Pass {
     // Inline the clock-only circuit up to the specified top module
     val modulesToInline = (c.modules.collect { case Module(_, n, _, _) if n != top => ModuleName(n, CircuitName(c.main)) }).toSet
     val inlineTransform = new InlineInstances
-    val inlinedCircuit = inlineTransform.run(onlyClockCircuit, modulesToInline, Set()).circuit
+    val inlinedCircuit = inlineTransform.run(onlyClockCircuit, modulesToInline, Set(), None).circuit
     val topModule = inlinedCircuit.modules.find(_.name == top).getOrElse(throwInternalError)
 
     // Build a hashmap of connections to use for getOrigins
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
index 8b5a0627..b04171a7 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala
@@ -69,8 +69,8 @@ class ClockListTransform extends Transform {
       val outputFile = new PrintWriter(out)
       val newC = (new ClockList(top, outputFile)).run(state.circuit)
       outputFile.close()
-      CircuitState(newC, state.form)
-    case Nil => CircuitState(state.circuit, state.form)
+      CircuitState(newC, state.form, state.annotations)
+    case Nil => state
     case seq => error(s"Found illegal clock list annotation(s): $seq")
   }
 }
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
index 554c1f0d..b941503f 100644
--- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
@@ -158,8 +158,8 @@ class InferReadWrite extends Transform with PassBased {
     ResolveGenders
   )
   def execute(state: CircuitState): CircuitState = getMyAnnotations(state) match {
-    case Nil => CircuitState(state.circuit, state.form)
+    case Nil => state
     case Seq(InferReadWriteAnnotation(CircuitName(state.circuit.main))) =>
-      CircuitState(runPasses(state.circuit), state.form)
+      state.copy(circuit = runPasses(state.circuit))
   }
 }
diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
index 1659cf22..0c12d2aa 100644
--- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
+++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
@@ -110,7 +110,7 @@ Optional Arguments:
 class SimpleTransform(p: Pass, form: CircuitForm) extends Transform {
   def inputForm = form
   def outputForm = form
-  def execute(state: CircuitState): CircuitState = CircuitState(p.run(state.circuit), state.form)
+  def execute(state: CircuitState): CircuitState = CircuitState(p.run(state.circuit), state.form, state.annotations)
 }
 
 class SimpleMidTransform(p: Pass) extends SimpleTransform(p, MidForm)
@@ -143,12 +143,12 @@ class ReplSeqMem extends Transform with SimpleRun {
           Some(AnnotationMap(ann.annotations ++ curState.annotations.get.annotations))
       }
       CircuitState(res.circuit, res.form, newAnnotations)
-    }).copy(annotations = None)
+    })
   }
 
   def execute(state: CircuitState): CircuitState =
     getMyAnnotations(state) match {
-      case Nil => state.copy(annotations = None) // Do nothing if there are no annotations
+      case Nil => state // Do nothing if there are no annotations
       case p => (p.collectFirst { case a if (a.target == CircuitName(state.circuit.main)) => a }) match {
         case Some(ReplSeqMemAnnotation(target, inputFileName, outputConfig)) =>
           val inConfigFile = {
diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
index a4f7245b..5a35d85c 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
@@ -69,7 +69,7 @@ class WiringTransform extends Transform with SimpleRun {
         ResolveKinds,
         ResolveGenders)
   def execute(state: CircuitState): CircuitState = getMyAnnotations(state) match {
-    case Nil => CircuitState(state.circuit, state.form)
+    case Nil => state
     case p => 
       val sinks = mutable.HashMap[String, Set[String]]()
       val sources = mutable.HashMap[String, String]()
@@ -84,12 +84,12 @@ class WiringTransform extends Transform with SimpleRun {
         case TopAnnotation(m, pin) => tops(pin) = m.name
       }
       (sources.size, tops.size, sinks.size, comp.size) match {
-        case (0, 0, p, 0) => state.copy(annotations = None)
+        case (0, 0, p, 0) => state
         case (s, t, p, c) if (p > 0) & (s == t) & (t == c) =>
           val wis = tops.foldLeft(Seq[WiringInfo]()) { case (seq, (pin, top)) =>
             seq :+ WiringInfo(sources(pin), comp(pin), sinks("pin:" + pin), pin, top)
           }
-          state.copy(circuit = runPasses(state.circuit, passSeq(wis)), annotations = None)
+          state.copy(circuit = runPasses(state.circuit, passSeq(wis)))
         case _ => error("Wrong number of sources, tops, or sinks!")
       }
   }