clean up Utils.scala

remove unnecessary functions & change spaces

7 files changed, 76 insertions, 61 deletions

diff --git a/src/main/scala/firrtl/passes/CheckChirrtl.scala b/src/main/scala/firrtl/passes/CheckChirrtl.scala
index 60a49bac..e0e7c57a 100644
--- a/src/main/scala/firrtl/passes/CheckChirrtl.scala
+++ b/src/main/scala/firrtl/passes/CheckChirrtl.scala
@@ -105,7 +105,7 @@ object CheckChirrtl extends Pass with LazyLogging {
         e
       }
       def checkChirrtlS(s: Statement): Statement = {
-        sinfo = s.getInfo
+        sinfo = get_info(s)
         def checkName(name: String): String = {
           if (names.contains(name)) errors.append(new NotUniqueException(name))
           else names(name) = true
@@ -138,7 +138,7 @@ object CheckChirrtl extends Pass with LazyLogging {
       for (p <- m.ports) {
         sinfo = p.info
         names(p.name) = true
-        val tpe = p.getType
+        val tpe = p.tpe
         tpe map (checkChirrtlT)
         tpe map (checkChirrtlW)
       }
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index e61c55ea..6e49ce93 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -241,7 +241,7 @@ object CheckHighForm extends Pass with LazyLogging {
           else names(name) = true
           name 
         }
-        sinfo = s.getInfo
+        sinfo = get_info(s)
 
         s map (checkName)
         s map (checkHighFormT)
@@ -276,7 +276,7 @@ object CheckHighForm extends Pass with LazyLogging {
       for (p <- m.ports) {
         // FIXME should we set sinfo here?
         names(p.name) = true
-        val tpe = p.getType
+        val tpe = p.tpe
         tpe map (checkHighFormT)
         tpe map (checkHighFormW)
       }
@@ -343,20 +343,29 @@ object CheckTypes extends Pass with LazyLogging {
       def all_ground (ls:Seq[Expression]) : Unit = {
          var error = false
          for (x <- ls ) {
-            if (!(x.tpe.typeof[UIntType] || x.tpe.typeof[SIntType])) error = true
+            x.tpe match {
+              case _: UIntType | _: SIntType =>
+              case _ => error = true
+            }
          }
          if (error) errors.append(new OpNotGround(info,e.op.serialize))
       }
       def all_uint (ls:Seq[Expression]) : Unit = {
          var error = false
          for (x <- ls ) {
-            if (!(x.tpe.typeof[UIntType])) error = true
+            x.tpe match {
+              case _: UIntType =>
+              case _ => error = true
+            }
          }
          if (error) errors.append(new OpNotAllUInt(info,e.op.serialize))
       }
       def is_uint (x:Expression) : Unit = {
          var error = false
-         if (!(x.tpe.typeof[UIntType])) error = true
+         x.tpe match {
+           case _: UIntType =>
+           case _ => error = true
+         }
          if (error) errors.append(new OpNotUInt(info,e.op.serialize,x.serialize))
       }
       
@@ -447,11 +456,17 @@ object CheckTypes extends Pass with LazyLogging {
             case (e:Mux) => {
                if (wt(e.tval.tpe) != wt(e.fval.tpe)) errors.append(new MuxSameType(info))
                if (!passive(e.tpe)) errors.append(new MuxPassiveTypes(info))
-               if (!(e.cond.tpe.typeof[UIntType])) errors.append(new MuxCondUInt(info))
+               e.cond.tpe match {
+                 case _: UIntType =>
+                 case _ => errors.append(new MuxCondUInt(info))
+               }
             }
             case (e:ValidIf) => {
                if (!passive(e.tpe)) errors.append(new ValidIfPassiveTypes(info))
-               if (!(e.cond.tpe.typeof[UIntType])) errors.append(new ValidIfCondUInt(info))
+               e.cond.tpe match {
+                 case _: UIntType =>
+                 case _ => errors.append(new ValidIfCondUInt(info))
+               }
             }
             case (_:UIntLiteral | _:SIntLiteral) => false
          }
@@ -597,7 +612,7 @@ object CheckGenders extends Pass {
          (e) match { 
             case (e:WRef) => genders(e.name)
             case (e:WSubField) => 
-               val f = e.exp.tpe.as[BundleType].get.fields.find(f => f.name == e.name).get
+               val f = e.exp.tpe.asInstanceOf[BundleType].fields.find(f => f.name == e.name).get
                times(get_gender(e.exp,genders),f.flip)
             case (e:WSubIndex) => get_gender(e.exp,genders)
             case (e:WSubAccess) => get_gender(e.exp,genders)
@@ -735,7 +750,7 @@ object CheckWidths extends Pass {
          }
          def check_width_s (s:Statement) : Statement = {
             s map (check_width_s) map (check_width_e(get_info(s)))
-            def tm (t:Type) : Type = mapr(check_width_w(info(s)) _,t)
+            def tm (t:Type) : Type = mapr(check_width_w(get_info(s)) _,t)
             s map (tm)
          }
       
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index 7793c85c..a8fda1bf 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -5,7 +5,6 @@ package passes
 import scala.collection.mutable
 
 import firrtl.Mappers.{ExpMap,StmtMap}
-import firrtl.Utils.WithAs
 import firrtl.ir._
 import firrtl.passes.{PassException,PassExceptions}
 import Annotations.{Loose, Unstable, Annotation, TransID, Named, ModuleName, ComponentName, CircuitName, AnnotationMap}
diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala
index e5661fae..a4c584ed 100644
--- a/src/main/scala/firrtl/passes/LowerTypes.scala
+++ b/src/main/scala/firrtl/passes/LowerTypes.scala
@@ -105,15 +105,15 @@ object LowerTypes extends Pass {
           require(tail.isEmpty) // there can't be a tail for these
           val memType = memDataTypeMap(mem.name)
 
-          if (memType.isGround) {
-            Seq(e)
-          } else {
-            val exps = create_exps(mem.name, memType)
-            exps map { e =>
-              val loMemName = loweredName(e)
-              val loMem = WRef(loMemName, UnknownType, kind(mem), UNKNOWNGENDER)
-              mergeRef(loMem, mergeRef(port, field))
-            }
+          memType match {
+            case _: GroundType => Seq(e)
+            case _ =>
+              val exps = create_exps(mem.name, memType)
+              exps map { e =>
+                val loMemName = loweredName(e)
+                val loMem = WRef(loMemName, UnknownType, kind(mem), UNKNOWNGENDER)
+                mergeRef(loMem, mergeRef(port, field))
+              }
           }
         // Fields that need not be replicated for each
         // eg. mem.reader.data[0].a
@@ -158,26 +158,26 @@ object LowerTypes extends Pass {
         s map lowerTypesStmt match {
           case s: DefWire =>
             sinfo = s.info
-            if (s.tpe.isGround) {
-              s
-            } else {
-              val exps = create_exps(s.name, s.tpe)
-              val stmts = exps map (e => DefWire(s.info, loweredName(e), e.tpe))
-              Block(stmts)
+            s.tpe match {
+              case _: GroundType => s
+              case _ =>
+                val exps = create_exps(s.name, s.tpe)
+                val stmts = exps map (e => DefWire(s.info, loweredName(e), e.tpe))
+                Block(stmts)
             }
           case s: DefRegister =>
             sinfo = s.info
-            if (s.tpe.isGround) {
-              s map lowerTypesExp
-            } else {
-              val es = create_exps(s.name, s.tpe)
-              val inits = create_exps(s.init) map (lowerTypesExp)
-              val clock = lowerTypesExp(s.clock)
-              val reset = lowerTypesExp(s.reset)
-              val stmts = es zip inits map { case (e, i) =>
-                DefRegister(s.info, loweredName(e), e.tpe, clock, reset, i)
-              }
-              Block(stmts)
+            s.tpe match {
+              case _: GroundType => s map lowerTypesExp
+              case _ =>
+                val es = create_exps(s.name, s.tpe)
+                val inits = create_exps(s.init) map (lowerTypesExp)
+                val clock = lowerTypesExp(s.clock)
+                val reset = lowerTypesExp(s.reset)
+                val stmts = es zip inits map { case (e, i) =>
+                  DefRegister(s.info, loweredName(e), e.tpe, clock, reset, i)
+                }
+                Block(stmts)
             }
           // Could instead just save the type of each Module as it gets processed
           case s: WDefInstance =>
@@ -188,7 +188,7 @@ object LowerTypes extends Pass {
                   val exps = create_exps(WRef(f.name, f.tpe, ExpKind(), times(f.flip, MALE)))
                   exps map ( e =>
                     // Flip because inst genders are reversed from Module type
-                    Field(loweredName(e), toFlip(gender(e)).flip, e.tpe)
+                    Field(loweredName(e), swap(to_flip(gender(e))), e.tpe)
                   )
                 }
                 WDefInstance(s.info, s.name, s.module, BundleType(fieldsx))
@@ -197,16 +197,16 @@ object LowerTypes extends Pass {
           case s: DefMemory =>
             sinfo = s.info
             memDataTypeMap += (s.name -> s.dataType)
-            if (s.dataType.isGround) {
-              s
-            } else {
-              val exps = create_exps(s.name, s.dataType)
-              val stmts = exps map { e =>
-                DefMemory(s.info, loweredName(e), e.tpe, s.depth,
-                  s.writeLatency, s.readLatency, s.readers, s.writers,
-                  s.readwriters)
-              }
-              Block(stmts)
+            s.dataType match {
+              case _: GroundType => s
+              case _ =>
+                val exps = create_exps(s.name, s.dataType)
+                val stmts = exps map { e =>
+                  DefMemory(s.info, loweredName(e), e.tpe, s.depth,
+                    s.writeLatency, s.readLatency, s.readers, s.writers,
+                    s.readwriters)
+                }
+                Block(stmts)
             }
           // wire foo : { a , b }
           // node x = foo
diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala
index a3ce49f7..880d6b1c 100644
--- a/src/main/scala/firrtl/passes/RemoveAccesses.scala
+++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala
@@ -76,7 +76,7 @@ object RemoveAccesses extends Pass {
       def onStmt(s: Statement): Statement = {
         def create_temp(e: Expression): (Statement, Expression) = {
           val n = namespace.newTemp
-          (DefWire(info(s), n, e.tpe), WRef(n, e.tpe, kind(e), gender(e)))
+          (DefWire(get_info(s), n, e.tpe), WRef(n, e.tpe, kind(e), gender(e)))
         }
 
         /** Replaces a subaccess in a given male expression
@@ -94,9 +94,9 @@ object RemoveAccesses extends Pass {
                 stmts += wire
                 rs.zipWithIndex foreach {
                   case (x, i) if i < temps.size =>
-                    stmts += Connect(info(s),getTemp(i),x.base)
+                    stmts += Connect(get_info(s),getTemp(i),x.base)
                   case (x, i) =>
-                    stmts += Conditionally(info(s),x.guard,Connect(info(s),getTemp(i),x.base),EmptyStmt)
+                    stmts += Conditionally(get_info(s),x.guard,Connect(get_info(s),getTemp(i),x.base),EmptyStmt)
                 }
                 temp
             }
diff --git a/src/main/scala/firrtl/passes/SplitExpressions.scala b/src/main/scala/firrtl/passes/SplitExpressions.scala
index 12d9982b..3b6021ed 100644
--- a/src/main/scala/firrtl/passes/SplitExpressions.scala
+++ b/src/main/scala/firrtl/passes/SplitExpressions.scala
@@ -2,7 +2,7 @@ package firrtl
 package passes
 
 import firrtl.Mappers.{ExpMap, StmtMap}
-import firrtl.Utils.{kind, gender, info}
+import firrtl.Utils.{kind, gender, get_info}
 import firrtl.ir._
 import scala.collection.mutable
 
@@ -20,17 +20,17 @@ object SplitExpressions extends Pass {
          def split(e: Expression): Expression = e match {
             case e: DoPrim => {
                val name = namespace.newTemp
-               v += DefNode(info(s), name, e)
+               v += DefNode(get_info(s), name, e)
                WRef(name, e.tpe, kind(e), gender(e))
             }
             case e: Mux => {
                val name = namespace.newTemp
-               v += DefNode(info(s), name, e)
+               v += DefNode(get_info(s), name, e)
                WRef(name, e.tpe, kind(e), gender(e))
             }
             case e: ValidIf => {
                val name = namespace.newTemp
-               v += DefNode(info(s), name, e)
+               v += DefNode(get_info(s), name, e)
                WRef(name, e.tpe, kind(e), gender(e))
             }
             case e => e
diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala
index b1a20fdd..d034719a 100644
--- a/src/main/scala/firrtl/passes/Uniquify.scala
+++ b/src/main/scala/firrtl/passes/Uniquify.scala
@@ -109,8 +109,9 @@ object Uniquify extends Pass {
           val newName = findValidPrefix(f.name, Seq(""), namespace)
           namespace += newName
           Field(newName, f.flip, f.tpe)
-        } map { f =>
-          if (f.tpe.isAggregate) {
+        } map { f => f.tpe match {
+          case _: GroundType => f
+          case _ =>
             val tpe = recUniquifyNames(f.tpe, collection.mutable.HashSet())
             val elts = enumerateNames(tpe)
             // Need leading _ for findValidPrefix, it doesn't add _ for checks
@@ -123,8 +124,6 @@ object Uniquify extends Pass {
             }
             namespace ++= (elts map (e => LowerTypes.loweredName(prefix +: e)))
             Field(prefix, f.flip, tpe)
-          } else {
-            f
           }
         }
         BundleType(newFields)
@@ -349,7 +348,9 @@ object Uniquify extends Pass {
 
     def uniquifyPorts(m: DefModule): DefModule = {
       def uniquifyPorts(ports: Seq[Port]): Seq[Port] = {
-        val portsType = BundleType(ports map (_.toField))
+        val portsType = BundleType(ports map {
+          case Port(_, name, dir, tpe) => Field(name, to_flip(dir), tpe)
+        })
         val uniquePortsType = uniquifyNames(portsType, collection.mutable.HashSet())
         val localMap = createNameMapping(portsType, uniquePortsType)
         portNameMap += (m.name -> localMap)