Rename gender to flow

The following names are changed:
  - gender        -> flow
  - Gender        -> Flow
  - MALE          -> SourceFlow
  - FEMALE        -> SinkFlow
  - BIGENDER      -> DuplexFlow
  - UNKNOWNGENDER -> UnknownFlow

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

20 files changed, 191 insertions, 193 deletions

diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala
index d1b6a03f..9fbf3eeb 100644
--- a/src/main/scala/firrtl/passes/CheckInitialization.scala
+++ b/src/main/scala/firrtl/passes/CheckInitialization.scala
@@ -18,14 +18,14 @@ object CheckInitialization extends Pass {
   private case class VoidExpr(stmt: Statement, voidDeps: Seq[Expression])
 
   class RefNotInitializedException(info: Info, mname: String, name: String, trace: Seq[Statement]) extends PassException(
-      s"$info : [module $mname]  Reference $name is not fully initialized.\n" + 
+      s"$info : [module $mname]  Reference $name is not fully initialized.\n" +
       trace.map(s => s"  ${get_info(s)} : ${s.serialize}").mkString("\n")
     )
 
   private def getTrace(expr: WrappedExpression, voidExprs: Map[WrappedExpression, VoidExpr]): Seq[Statement] = {
     @tailrec
     def rec(e: WrappedExpression, map: Map[WrappedExpression, VoidExpr], trace: Seq[Statement]): Seq[Statement] = {
-      val voidExpr = map(e) 
+      val voidExpr = map(e)
       val newTrace = voidExpr.stmt +: trace
       if (voidExpr.voidDeps.nonEmpty) rec(voidExpr.voidDeps.head, map, newTrace) else newTrace
     }
@@ -62,7 +62,7 @@ object CheckInitialization extends Pass {
           case node: DefNode =>
             val (hasVoid, voidDeps) = hasVoidExpr(node.value)
             if (hasVoid) {
-              val nodeRef = WRef(node.name, node.value.tpe, NodeKind, MALE)
+              val nodeRef = WRef(node.name, node.value.tpe, NodeKind, SourceFlow)
               voidExprs(nodeRef) = VoidExpr(node, voidDeps)
             }
           case sx => sx.foreach(checkInitS)
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index a17a5a2e..5f58b7f1 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -221,12 +221,12 @@ trait CheckHighFormLike {
 
     // Search for ResetType Ports of direction
     def findBadResetTypePorts(m: DefModule, dir: Direction): Seq[(Port, Expression)] = {
-      val bad = to_gender(dir)
+      val bad = to_flow(dir)
       for {
         port <- m.ports
-        ref = WRef(port).copy(gender = to_gender(port.direction))
+        ref = WRef(port).copy(flow = to_flow(port.direction))
         expr <- create_exps(ref)
-        if ((expr.tpe == ResetType) && (gender(expr) == bad))
+        if ((expr.tpe == ResetType) && (flow(expr) == bad))
       } yield (port, expr)
     }
 
@@ -544,31 +544,31 @@ object CheckTypes extends Pass {
   }
 }
 
-object CheckGenders extends Pass {
-  type GenderMap = collection.mutable.HashMap[String, Gender]
+object CheckFlows extends Pass {
+  type FlowMap = collection.mutable.HashMap[String, Flow]
 
-  implicit def toStr(g: Gender): String = g match {
-    case MALE => "source"
-    case FEMALE => "sink"
-    case UNKNOWNGENDER => "unknown"
-    case BIGENDER => "sourceOrSink"
+  implicit def toStr(g: Flow): String = g match {
+    case SourceFlow => "source"
+    case SinkFlow => "sink"
+    case UnknownFlow => "unknown"
+    case DuplexFlow => "sourceOrSink"
   }
 
-  class WrongGender(info:Info, mname: String, expr: String, wrong: Gender, right: Gender) extends PassException(
+  class WrongFlow(info:Info, mname: String, expr: String, wrong: Flow, right: Flow) extends PassException(
     s"$info: [module $mname]  Expression $expr is used as a $wrong but can only be used as a $right.")
 
   def run (c:Circuit): Circuit = {
     val errors = new Errors()
 
-    def get_gender(e: Expression, genders: GenderMap): Gender = e match {
-      case (e: WRef) => genders(e.name)
-      case (e: WSubIndex) => get_gender(e.expr, genders)
-      case (e: WSubAccess) => get_gender(e.expr, genders)
+    def get_flow(e: Expression, flows: FlowMap): Flow = e match {
+      case (e: WRef) => flows(e.name)
+      case (e: WSubIndex) => get_flow(e.expr, flows)
+      case (e: WSubAccess) => get_flow(e.expr, flows)
       case (e: WSubField) => e.expr.tpe match {case t: BundleType =>
         val f = (t.fields find (_.name == e.name)).get
-        times(get_gender(e.expr, genders), f.flip)
+        times(get_flow(e.expr, flows), f.flip)
       }
-      case _ => MALE
+      case _ => SourceFlow
     }
 
     def flip_q(t: Type): Boolean = {
@@ -582,64 +582,64 @@ object CheckGenders extends Pass {
       flip_rec(t, Default)
     }
 
-    def check_gender(info:Info, mname: String, genders: GenderMap, desired: Gender)(e:Expression): Unit = {
-      val gender = get_gender(e,genders)
-      (gender, desired) match {
-        case (MALE, FEMALE) =>
-          errors.append(new WrongGender(info, mname, e.serialize, desired, gender))
-        case (FEMALE, MALE) => kind(e) match {
+    def check_flow(info:Info, mname: String, flows: FlowMap, desired: Flow)(e:Expression): Unit = {
+      val flow = get_flow(e,flows)
+      (flow, desired) match {
+        case (SourceFlow, SinkFlow) =>
+          errors.append(new WrongFlow(info, mname, e.serialize, desired, flow))
+        case (SinkFlow, SourceFlow) => kind(e) match {
           case PortKind | InstanceKind if !flip_q(e.tpe) => // OK!
           case _ =>
-            errors.append(new WrongGender(info, mname, e.serialize, desired, gender))
+            errors.append(new WrongFlow(info, mname, e.serialize, desired, flow))
         }
         case _ =>
       }
    }
 
-    def check_genders_e (info:Info, mname: String, genders: GenderMap)(e:Expression): Unit = {
+    def check_flows_e (info:Info, mname: String, flows: FlowMap)(e:Expression): Unit = {
       e match {
-        case e: Mux => e foreach check_gender(info, mname, genders, MALE)
-        case e: DoPrim => e.args foreach check_gender(info, mname, genders, MALE)
+        case e: Mux => e foreach check_flow(info, mname, flows, SourceFlow)
+        case e: DoPrim => e.args foreach check_flow(info, mname, flows, SourceFlow)
         case _ =>
       }
-      e foreach check_genders_e(info, mname, genders)
+      e foreach check_flows_e(info, mname, flows)
     }
 
-    def check_genders_s(minfo: Info, mname: String, genders: GenderMap)(s: Statement): Unit = {
+    def check_flows_s(minfo: Info, mname: String, flows: FlowMap)(s: Statement): Unit = {
       val info = get_info(s) match { case NoInfo => minfo case x => x }
       s match {
-        case (s: DefWire) => genders(s.name) = BIGENDER
-        case (s: DefRegister) => genders(s.name) = BIGENDER
-        case (s: DefMemory) => genders(s.name) = MALE
-        case (s: WDefInstance) => genders(s.name) = MALE
+        case (s: DefWire) => flows(s.name) = DuplexFlow
+        case (s: DefRegister) => flows(s.name) = DuplexFlow
+        case (s: DefMemory) => flows(s.name) = SourceFlow
+        case (s: WDefInstance) => flows(s.name) = SourceFlow
         case (s: DefNode) =>
-          check_gender(info, mname, genders, MALE)(s.value)
-          genders(s.name) = MALE
+          check_flow(info, mname, flows, SourceFlow)(s.value)
+          flows(s.name) = SourceFlow
         case (s: Connect) =>
-          check_gender(info, mname, genders, FEMALE)(s.loc)
-          check_gender(info, mname, genders, MALE)(s.expr)
+          check_flow(info, mname, flows, SinkFlow)(s.loc)
+          check_flow(info, mname, flows, SourceFlow)(s.expr)
         case (s: Print) =>
-          s.args foreach check_gender(info, mname, genders, MALE)
-          check_gender(info, mname, genders, MALE)(s.en)
-          check_gender(info, mname, genders, MALE)(s.clk)
+          s.args foreach check_flow(info, mname, flows, SourceFlow)
+          check_flow(info, mname, flows, SourceFlow)(s.en)
+          check_flow(info, mname, flows, SourceFlow)(s.clk)
         case (s: PartialConnect) =>
-          check_gender(info, mname, genders, FEMALE)(s.loc)
-          check_gender(info, mname, genders, MALE)(s.expr)
+          check_flow(info, mname, flows, SinkFlow)(s.loc)
+          check_flow(info, mname, flows, SourceFlow)(s.expr)
         case (s: Conditionally) =>
-          check_gender(info, mname, genders, MALE)(s.pred)
+          check_flow(info, mname, flows, SourceFlow)(s.pred)
         case (s: Stop) =>
-          check_gender(info, mname, genders, MALE)(s.en)
-          check_gender(info, mname, genders, MALE)(s.clk)
+          check_flow(info, mname, flows, SourceFlow)(s.en)
+          check_flow(info, mname, flows, SourceFlow)(s.clk)
         case _ =>
       }
-      s foreach check_genders_e(info, mname, genders)
-      s foreach check_genders_s(minfo, mname, genders)
+      s foreach check_flows_e(info, mname, flows)
+      s foreach check_flows_s(minfo, mname, flows)
     }
 
     for (m <- c.modules) {
-      val genders = new GenderMap
-      genders ++= (m.ports map (p => p.name -> to_gender(p.direction)))
-      m foreach check_genders_s(m.info, m.name, genders)
+      val flows = new FlowMap
+      flows ++= (m.ports map (p => p.name -> to_flow(p.direction)))
+      m foreach check_flows_s(m.info, m.name, flows)
     }
     errors.trigger()
     c
diff --git a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
index f5b9d00c..3ba12b2d 100644
--- a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
+++ b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
@@ -13,10 +13,10 @@ object CommonSubexpressionElimination extends Pass {
     val nodes = collection.mutable.HashMap[String, Expression]()
 
     def eliminateNodeRef(e: Expression): Expression = e match {
-      case WRef(name, tpe, kind, gender) => nodes get name match {
+      case WRef(name, tpe, kind, flow) => nodes get name match {
         case Some(expression) => expressions get expression match {
           case Some(cseName) if cseName != name =>
-            WRef(cseName, tpe, kind, gender)
+            WRef(cseName, tpe, kind, flow)
           case _ => e
         }
         case _ => e
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index a8e2f2ac..12aa9690 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -108,18 +108,18 @@ object ExpandWhens extends Pass {
       // Return self, unchanged
       case stmt @ (_: DefNode | EmptyStmt) => stmt
       case w: DefWire =>
-        netlist ++= (getFemaleRefs(w.name, w.tpe, BIGENDER) map (ref => we(ref) -> WVoid))
+        netlist ++= (getFemaleRefs(w.name, w.tpe, DuplexFlow) map (ref => we(ref) -> WVoid))
         w
       case w: DefMemory =>
-        netlist ++= (getFemaleRefs(w.name, MemPortUtils.memType(w), MALE) map (ref => we(ref) -> WVoid))
+        netlist ++= (getFemaleRefs(w.name, MemPortUtils.memType(w), SourceFlow) map (ref => we(ref) -> WVoid))
         w
       case w: WDefInstance =>
-        netlist ++= (getFemaleRefs(w.name, w.tpe, MALE).map(ref => we(ref) -> WVoid))
+        netlist ++= (getFemaleRefs(w.name, w.tpe, SourceFlow).map(ref => we(ref) -> WVoid))
         w
       // Update netlist with self reference for each female reference
       // Return self, unchanged
       case r: DefRegister =>
-        netlist ++= (getFemaleRefs(r.name, r.tpe, BIGENDER) map (ref => we(ref) -> ref))
+        netlist ++= (getFemaleRefs(r.name, r.tpe, DuplexFlow) map (ref => we(ref) -> ref))
         r
       // For value assignments, update netlist/attaches and return EmptyStmt
       case c: Connect =>
@@ -193,12 +193,12 @@ object ExpandWhens extends Pass {
               EmptyStmt
             case _: ValidIf | _: Mux | _: DoPrim => nodes get res match {
               case Some(name) =>
-                netlist(lvalue) = WRef(name, res.tpe, NodeKind, MALE)
+                netlist(lvalue) = WRef(name, res.tpe, NodeKind, SourceFlow)
                 EmptyStmt
               case None =>
                 val name = namespace.newTemp
                 nodes(res) = name
-                netlist(lvalue) = WRef(name, res.tpe, NodeKind, MALE)
+                netlist(lvalue) = WRef(name, res.tpe, NodeKind, SourceFlow)
                 DefNode(sx.info, name, res)
             }
             case _ =>
@@ -213,7 +213,7 @@ object ExpandWhens extends Pass {
     val netlist = new Netlist
     // Add ports to netlist
     netlist ++= (m.ports flatMap { case Port(_, name, dir, tpe) =>
-      getFemaleRefs(name, tpe, to_gender(dir)) map (ref => we(ref) -> WVoid)
+      getFemaleRefs(name, tpe, to_flow(dir)) map (ref => we(ref) -> WVoid)
     })
     val bodyx = expandWhens(netlist, Seq(netlist), one)(m.body)
     (netlist, simlist, attaches, bodyx, infoMap)
@@ -221,13 +221,13 @@ object ExpandWhens extends Pass {
 
 
   /** Returns all references to all Female leaf subcomponents of a reference */
-  private def getFemaleRefs(n: String, t: Type, g: Gender): Seq[Expression] = {
+  private def getFemaleRefs(n: String, t: Type, g: Flow): Seq[Expression] = {
     val exps = create_exps(WRef(n, t, ExpKind, g))
     exps.flatMap { case exp =>
       exp.tpe match {
         case AnalogType(w) => None
-        case _ => gender(exp) match {
-          case (BIGENDER | FEMALE) => Some(exp)
+        case _ => flow(exp) match {
+          case (DuplexFlow | SinkFlow) => Some(exp)
           case _ => None
         }
       }
diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala
index 8f663afd..9c58da2c 100644
--- a/src/main/scala/firrtl/passes/InferWidths.scala
+++ b/src/main/scala/firrtl/passes/InferWidths.scala
@@ -182,18 +182,18 @@ class InferWidths extends Transform with ResolvedAnnotationPaths {
       rec(w)
       has
     }
- 
+
     //; Forward solve
     //; Returns a solved list where each constraint undergoes:
     //;  1) Continuous Solving (using triangular solving)
     //;  2) Remove Cycles
     //;  3) Move to solved if not self-recursive
     val u = make_unique(l)
-    
+
     //println("======== UNIQUE CONSTRAINTS ========")
     //for (x <- u) { println(x) }
     //println("====================================")
- 
+
     val f = new ConstraintMap
     val o = ArrayBuffer[String]()
     for ((n, e) <- u) {
@@ -219,10 +219,10 @@ class InferWidths extends Transform with ResolvedAnnotationPaths {
         o += n
       }
     }
- 
+
     //println("Forward Solved Constraints")
     //for (x <- f) println(x)
- 
+
     //; Backwards Solve
     val b = new ConstraintMap
     for (i <- (o.size - 1) to 0 by -1) {
@@ -281,7 +281,7 @@ class InferWidths extends Transform with ResolvedAnnotationPaths {
     }
 
     def get_constraints_declared_type (t: Type): Type = t match {
-      case FixedType(_, p) => 
+      case FixedType(_, p) =>
         v += WGeq(p,IntWidth(0))
         t
       case _ => t map get_constraints_declared_type
@@ -293,7 +293,7 @@ class InferWidths extends Transform with ResolvedAnnotationPaths {
           val locs = create_exps(s.loc)
           val exps = create_exps(s.expr)
           v ++= locs.zip(exps).flatMap { case (locx, expx) =>
-            to_flip(gender(locx)) match {
+            to_flip(flow(locx)) match {
               case Default => get_constraints_t(locx.tpe, expx.tpe)//WGeq(getWidth(locx), getWidth(expx))
               case Flip => get_constraints_t(expx.tpe, locx.tpe)//WGeq(getWidth(expx), getWidth(locx))
             }
@@ -305,7 +305,7 @@ class InferWidths extends Transform with ResolvedAnnotationPaths {
           v ++= (ls flatMap {case (x, y) =>
             val locx = locs(x)
             val expx = exps(y)
-            to_flip(gender(locx)) match {
+            to_flip(flow(locx)) match {
               case Default => get_constraints_t(locx.tpe, expx.tpe)//WGeq(getWidth(locx), getWidth(expx))
               case Flip => get_constraints_t(expx.tpe, locx.tpe)//WGeq(getWidth(expx), getWidth(locx))
             }
@@ -317,7 +317,7 @@ class InferWidths extends Transform with ResolvedAnnotationPaths {
                get_constraints_t(UIntType(IntWidth(1)), s.reset.tpe))
            }
           v ++= get_constraints_t(s.tpe, s.init.tpe)
-        case (s:Conditionally) => v ++= 
+        case (s:Conditionally) => v ++=
            get_constraints_t(s.pred.tpe, UIntType(IntWidth(1))) ++
            get_constraints_t(UIntType(IntWidth(1)), s.pred.tpe)
         case Attach(_, exprs) =>
diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala
index 8035c1ce..f52e1e6b 100644
--- a/src/main/scala/firrtl/passes/LowerTypes.scala
+++ b/src/main/scala/firrtl/passes/LowerTypes.scala
@@ -39,21 +39,21 @@ object LowerTypes extends Transform {
   }
   def loweredName(s: Seq[String]): String = s mkString delim
   def renameExps(renames: RenameMap, n: String, t: Type, root: String): Seq[String] =
-    renameExps(renames, WRef(n, t, ExpKind, UNKNOWNGENDER), root)
+    renameExps(renames, WRef(n, t, ExpKind, UnknownFlow), root)
   def renameExps(renames: RenameMap, n: String, t: Type): Seq[String] =
-    renameExps(renames, WRef(n, t, ExpKind, UNKNOWNGENDER), "")
+    renameExps(renames, WRef(n, t, ExpKind, UnknownFlow), "")
   def renameExps(renames: RenameMap, e: Expression, root: String): Seq[String] = e.tpe match {
     case (_: GroundType) =>
       val name = root + loweredName(e)
       renames.rename(root + e.serialize, name)
       Seq(name)
     case (t: BundleType) => t.fields.flatMap { f =>
-      val subNames = renameExps(renames, WSubField(e, f.name, f.tpe, times(gender(e), f.flip)), root)
+      val subNames = renameExps(renames, WSubField(e, f.name, f.tpe, times(flow(e), f.flip)), root)
       renames.rename(root + e.serialize, subNames)
       subNames
     }
     case (t: VectorType) => (0 until t.size).flatMap { i =>
-      val subNames = renameExps(renames, WSubIndex(e, i, t.tpe,gender(e)), root)
+      val subNames = renameExps(renames, WSubIndex(e, i, t.tpe,flow(e)), root)
       renames.rename(root + e.serialize, subNames)
       subNames
     }
@@ -67,14 +67,14 @@ object LowerTypes extends Transform {
       renames.rename(hiRef.serialize, loRef.serialize)
       Seq(loRef.serialize)
     case (t: BundleType) => t.fields.foldLeft(Seq[String]()){(names, f) =>
-      val subNames = renameMemExps(renames, WSubField(e, f.name, f.tpe, times(gender(e), f.flip)), portAndField)
+      val subNames = renameMemExps(renames, WSubField(e, f.name, f.tpe, times(flow(e), f.flip)), portAndField)
       val (mem, tail) = splitRef(e)
       val hiRef = mergeRef(mem, mergeRef(portAndField, tail))
       renames.rename(hiRef.serialize, subNames)
       names ++ subNames
     }
     case (t: VectorType) => (0 until t.size).foldLeft(Seq[String]()){(names, i) =>
-      val subNames = renameMemExps(renames, WSubIndex(e, i, t.tpe,gender(e)), portAndField)
+      val subNames = renameMemExps(renames, WSubIndex(e, i, t.tpe,flow(e)), portAndField)
       val (mem, tail) = splitRef(e)
       val hiRef = mergeRef(mem, mergeRef(portAndField, tail))
       renames.rename(hiRef.serialize, subNames)
@@ -116,7 +116,7 @@ object LowerTypes extends Transform {
           case _: GroundType => Seq(e)
           case memType => create_exps(mem.name, memType) map { e =>
             val loMemName = loweredName(e)
-            val loMem = WRef(loMemName, UnknownType, kind(mem), UNKNOWNGENDER)
+            val loMem = WRef(loMemName, UnknownType, kind(mem), UnknownFlow)
             mergeRef(loMem, mergeRef(port, field))
           }
         }
@@ -128,7 +128,7 @@ object LowerTypes extends Transform {
           case Some(ex) =>
             val loMemExp = mergeRef(mem, ex)
             val loMemName = loweredName(loMemExp)
-            WRef(loMemName, UnknownType, kind(mem), UNKNOWNGENDER)
+            WRef(loMemName, UnknownType, kind(mem), UnknownFlow)
           case None => mem
         }
         Seq(mergeRef(loMem, mergeRef(port, field)))
@@ -143,15 +143,15 @@ object LowerTypes extends Transform {
       case InstanceKind =>
         val (root, tail) = splitRef(e)
         val name = loweredName(tail)
-        WSubField(root, name, e.tpe, gender(e))
+        WSubField(root, name, e.tpe, flow(e))
       case MemKind =>
         val exps = lowerTypesMemExp(memDataTypeMap, info, mname)(e)
         exps.size match {
           case 1 => exps.head
-          case _ => error("Error! lowerTypesExp called on MemKind " + 
+          case _ => error("Error! lowerTypesExp called on MemKind " +
                           "SubField that needs to be expanded!")(info, mname)
         }
-      case _ => WRef(loweredName(e), e.tpe, kind(e), gender(e))
+      case _ => WRef(loweredName(e), e.tpe, kind(e), flow(e))
     }
     case e: Mux => e map lowerTypesExp(memDataTypeMap, info, mname)
     case e: ValidIf => e map lowerTypesExp(memDataTypeMap, info, mname)
@@ -164,11 +164,11 @@ object LowerTypes extends Transform {
     s map lowerTypesStmt(memDataTypeMap, info, mname, renames) match {
       case s: DefWire => s.tpe match {
         case _: GroundType => s
-        case _ => 
+        case _ =>
           val exps = create_exps(s.name, s.tpe)
           val names = exps map loweredName
           renameExps(renames, s.name, s.tpe)
-          Block((exps zip names) map { case (e, n) => 
+          Block((exps zip names) map { case (e, n) =>
             DefWire(s.info, n, e.tpe)
           })
       }
@@ -190,9 +190,9 @@ object LowerTypes extends Transform {
         case t: BundleType =>
           val fieldsx = t.fields flatMap { f =>
             renameExps(renames, f.name, f.tpe, s"${sx.name}.")
-            create_exps(WRef(f.name, f.tpe, ExpKind, times(f.flip, MALE))) map { e => 
-              // Flip because inst genders are reversed from Module type
-              Field(loweredName(e), swap(to_flip(gender(e))), e.tpe)
+            create_exps(WRef(f.name, f.tpe, ExpKind, times(f.flip, SourceFlow))) map { e =>
+              // Flip because inst flows are reversed from Module type
+              Field(loweredName(e), swap(to_flip(flow(e))), e.tpe)
             }
           }
           WDefInstance(sx.info, sx.name, sx.module, BundleType(fieldsx))
@@ -262,11 +262,11 @@ object LowerTypes extends Transform {
     renames.setModule(m.name)
     // Lower Ports
     val portsx = m.ports flatMap { p =>
-      val exps = create_exps(WRef(p.name, p.tpe, PortKind, to_gender(p.direction)))
+      val exps = create_exps(WRef(p.name, p.tpe, PortKind, to_flow(p.direction)))
       val names = exps map loweredName
       renameExps(renames, p.name, p.tpe)
       (exps zip names) map { case (e, n) =>
-        Port(p.info, n, to_dir(gender(e)), e.tpe)
+        Port(p.info, n, to_dir(flow(e)), e.tpe)
       }
     }
     m match {
@@ -285,4 +285,3 @@ object LowerTypes extends Transform {
     CircuitState(result, outputForm, state.annotations, Some(renames))
   }
 }
-
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 1428ea5f..9a644dc8 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -48,10 +48,10 @@ class Errors {
 // These should be distributed into separate files
 object ToWorkingIR extends Pass {
   def toExp(e: Expression): Expression = e map toExp match {
-    case ex: Reference => WRef(ex.name, ex.tpe, UnknownKind, UNKNOWNGENDER)
-    case ex: SubField => WSubField(ex.expr, ex.name, ex.tpe, UNKNOWNGENDER)
-    case ex: SubIndex => WSubIndex(ex.expr, ex.value, ex.tpe, UNKNOWNGENDER)
-    case ex: SubAccess => WSubAccess(ex.expr, ex.index, ex.tpe, UNKNOWNGENDER)
+    case ex: Reference => WRef(ex.name, ex.tpe, UnknownKind, UnknownFlow)
+    case ex: SubField => WSubField(ex.expr, ex.name, ex.tpe, UnknownFlow)
+    case ex: SubIndex => WSubIndex(ex.expr, ex.value, ex.tpe, UnknownFlow)
+    case ex: SubAccess => WSubAccess(ex.expr, ex.index, ex.tpe, UnknownFlow)
     case ex => ex // This might look like a case to use case _ => e, DO NOT!
   }
 
@@ -69,26 +69,26 @@ object PullMuxes extends Pass {
      def pull_muxes_e(e: Expression): Expression = e map pull_muxes_e match {
        case ex: WSubField => ex.expr match {
          case exx: Mux => Mux(exx.cond,
-           WSubField(exx.tval, ex.name, ex.tpe, ex.gender),
-           WSubField(exx.fval, ex.name, ex.tpe, ex.gender), ex.tpe)
+           WSubField(exx.tval, ex.name, ex.tpe, ex.flow),
+           WSubField(exx.fval, ex.name, ex.tpe, ex.flow), ex.tpe)
          case exx: ValidIf => ValidIf(exx.cond,
-           WSubField(exx.value, ex.name, ex.tpe, ex.gender), ex.tpe)
+           WSubField(exx.value, ex.name, ex.tpe, ex.flow), ex.tpe)
          case _ => ex  // case exx => exx causes failed tests
        }
        case ex: WSubIndex => ex.expr match {
          case exx: Mux => Mux(exx.cond,
-           WSubIndex(exx.tval, ex.value, ex.tpe, ex.gender),
-           WSubIndex(exx.fval, ex.value, ex.tpe, ex.gender), ex.tpe)
+           WSubIndex(exx.tval, ex.value, ex.tpe, ex.flow),
+           WSubIndex(exx.fval, ex.value, ex.tpe, ex.flow), ex.tpe)
          case exx: ValidIf => ValidIf(exx.cond,
-           WSubIndex(exx.value, ex.value, ex.tpe, ex.gender), ex.tpe)
+           WSubIndex(exx.value, ex.value, ex.tpe, ex.flow), ex.tpe)
          case _ => ex  // case exx => exx causes failed tests
        }
        case ex: WSubAccess => ex.expr match {
          case exx: Mux => Mux(exx.cond,
-           WSubAccess(exx.tval, ex.index, ex.tpe, ex.gender),
-           WSubAccess(exx.fval, ex.index, ex.tpe, ex.gender), ex.tpe)
+           WSubAccess(exx.tval, ex.index, ex.tpe, ex.flow),
+           WSubAccess(exx.fval, ex.index, ex.tpe, ex.flow), ex.tpe)
          case exx: ValidIf => ValidIf(exx.cond,
-           WSubAccess(exx.value, ex.index, ex.tpe, ex.gender), ex.tpe)
+           WSubAccess(exx.value, ex.index, ex.tpe, ex.flow), ex.tpe)
          case _ => ex  // case exx => exx causes failed tests
        }
        case ex => ex
@@ -105,29 +105,29 @@ object PullMuxes extends Pass {
 object ExpandConnects extends Pass {
   def run(c: Circuit): Circuit = {
     def expand_connects(m: Module): Module = {
-      val genders = collection.mutable.LinkedHashMap[String,Gender]()
+      val flows = collection.mutable.LinkedHashMap[String,Flow]()
       def expand_s(s: Statement): Statement = {
-        def set_gender(e: Expression): Expression = e map set_gender match {
-          case ex: WRef => WRef(ex.name, ex.tpe, ex.kind, genders(ex.name))
+        def set_flow(e: Expression): Expression = e map set_flow match {
+          case ex: WRef => WRef(ex.name, ex.tpe, ex.kind, flows(ex.name))
           case ex: WSubField =>
             val f = get_field(ex.expr.tpe, ex.name)
-            val genderx = times(gender(ex.expr), f.flip)
-            WSubField(ex.expr, ex.name, ex.tpe, genderx)
-          case ex: WSubIndex => WSubIndex(ex.expr, ex.value, ex.tpe, gender(ex.expr))
-          case ex: WSubAccess => WSubAccess(ex.expr, ex.index, ex.tpe, gender(ex.expr))
+            val flowx = times(flow(ex.expr), f.flip)
+            WSubField(ex.expr, ex.name, ex.tpe, flowx)
+          case ex: WSubIndex => WSubIndex(ex.expr, ex.value, ex.tpe, flow(ex.expr))
+          case ex: WSubAccess => WSubAccess(ex.expr, ex.index, ex.tpe, flow(ex.expr))
           case ex => ex
         }
         s match {
-          case sx: DefWire => genders(sx.name) = BIGENDER; sx
-          case sx: DefRegister => genders(sx.name) = BIGENDER; sx
-          case sx: WDefInstance => genders(sx.name) = MALE; sx
-          case sx: DefMemory => genders(sx.name) = MALE; sx
-          case sx: DefNode => genders(sx.name) = MALE; sx
+          case sx: DefWire => flows(sx.name) = DuplexFlow; sx
+          case sx: DefRegister => flows(sx.name) = DuplexFlow; sx
+          case sx: WDefInstance => flows(sx.name) = SourceFlow; sx
+          case sx: DefMemory => flows(sx.name) = SourceFlow; sx
+          case sx: DefNode => flows(sx.name) = SourceFlow; sx
           case sx: IsInvalid =>
             val invalids = create_exps(sx.expr).flatMap { case expx =>
-               gender(set_gender(expx)) match {
-                  case BIGENDER => Some(IsInvalid(sx.info, expx))
-                  case FEMALE => Some(IsInvalid(sx.info, expx))
+               flow(set_flow(expx)) match {
+                  case DuplexFlow => Some(IsInvalid(sx.info, expx))
+                  case SinkFlow => Some(IsInvalid(sx.info, expx))
                   case _ => None
                }
             }
@@ -140,7 +140,7 @@ object ExpandConnects extends Pass {
             val locs = create_exps(sx.loc)
             val exps = create_exps(sx.expr)
             Block(locs.zip(exps).map { case (locx, expx) =>
-               to_flip(gender(locx)) match {
+               to_flip(flow(locx)) match {
                   case Default => Connect(sx.info, locx, expx)
                   case Flip => Connect(sx.info, expx, locx)
                }
@@ -153,7 +153,7 @@ object ExpandConnects extends Pass {
               locs(x).tpe match {
                 case AnalogType(_) => Attach(sx.info, Seq(locs(x), exps(y)))
                 case _ =>
-                  to_flip(gender(locs(x))) match {
+                  to_flip(flow(locs(x))) match {
                     case Default => Connect(sx.info, locs(x), exps(y))
                     case Flip => Connect(sx.info, exps(y), locs(x))
                   }
@@ -164,7 +164,7 @@ object ExpandConnects extends Pass {
         }
       }
 
-      m.ports.foreach { p => genders(p.name) = to_gender(p.direction) }
+      m.ports.foreach { p => flows(p.name) = to_flow(p.direction) }
       Module(m.info, m.name, m.ports, expand_s(m.body))
     }
 
@@ -302,13 +302,13 @@ object VerilogPrep extends Pass {
   def run(c: Circuit): Circuit = {
     def lowerE(e: Expression): Expression = e match {
       case (_: WRef | _: WSubField) if kind(e) == InstanceKind =>
-        WRef(LowerTypes.loweredName(e), e.tpe, kind(e), gender(e))
+        WRef(LowerTypes.loweredName(e), e.tpe, kind(e), flow(e))
       case _ => e map lowerE
     }
 
     def lowerS(attachMap: AttachSourceMap)(s: Statement): Statement = s match {
       case WDefInstance(info, name, module, tpe) =>
-        val portRefs = create_exps(WRef(name, tpe, ExpKind, MALE))
+        val portRefs = create_exps(WRef(name, tpe, ExpKind, SourceFlow))
         val (portCons, wires) = portRefs.map { p =>
           attachMap.get(p) match {
             // If it has a source in attachMap use that
diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala
index 2cad4c36..1c2dc096 100644
--- a/src/main/scala/firrtl/passes/RemoveAccesses.scala
+++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala
@@ -85,7 +85,7 @@ class RemoveAccesses extends Pass {
       def onStmt(s: Statement): Statement = {
         def create_temp(e: Expression): (Statement, Expression) = {
           val n = namespace.newName(niceName(e))
-          (DefWire(get_info(s), n, e.tpe), WRef(n, e.tpe, kind(e), gender(e)))
+          (DefWire(get_info(s), n, e.tpe), WRef(n, e.tpe, kind(e), flow(e)))
         }
 
         /** Replaces a subaccess in a given male expression
@@ -134,7 +134,7 @@ class RemoveAccesses extends Pass {
           * Otherwise, map to children.
           */
         def fixMale(e: Expression): Expression = e match {
-          case w: WSubAccess => removeMale(WSubAccess(w.expr, fixMale(w.index), w.tpe, w.gender))
+          case w: WSubAccess => removeMale(WSubAccess(w.expr, fixMale(w.index), w.tpe, w.flow))
           //case w: WSubIndex => removeMale(w)
           //case w: WSubField => removeMale(w)
           case x => x map fixMale
@@ -145,7 +145,7 @@ class RemoveAccesses extends Pass {
           * Otherwise, map to children.
           */
         def fixFemale(e: Expression): Expression = e match {
-          case w: WSubAccess => WSubAccess(fixFemale(w.expr), fixMale(w.index), w.tpe, w.gender)
+          case w: WSubAccess => WSubAccess(fixFemale(w.expr), fixMale(w.index), w.tpe, w.flow)
           case x => x map fixFemale
         }
 
@@ -159,7 +159,7 @@ class RemoveAccesses extends Pass {
       }
       Module(m.info, m.name, m.ports, squashEmpty(onStmt(m.body)))
     }
-  
+
     c copy (modules = c.modules map {
       case m: ExtModule => m
       case m: Module => remove_m(m)
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
index 0ccb0b34..d0498cf0 100644
--- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
+++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
@@ -178,41 +178,41 @@ object RemoveCHIRRTL extends Transform {
     var has_write_mport = false
     var has_readwrite_mport: Option[Expression] = None
     var has_read_mport: Option[Expression] = None
-    def remove_chirrtl_e(g: Gender)(e: Expression): Expression = e match {
+    def remove_chirrtl_e(g: Flow)(e: Expression): Expression = e match {
       case Reference(name, tpe) => refs get name match {
         case Some(p) => g match {
-          case FEMALE =>
+          case SinkFlow =>
             has_write_mport = true
             if (p.rdwrite) has_readwrite_mport = Some(SubField(p.exp, "wmode", BoolType))
             SubField(p.exp, p.female, tpe)
-          case MALE =>
+          case SourceFlow =>
             SubField(p.exp, p.male, tpe)
         }
         case None => g match {
-          case FEMALE => raddrs get name match {
+          case SinkFlow => raddrs get name match {
             case Some(en) => has_read_mport = Some(en) ; e
             case None => e
           }
-          case MALE => e
+          case SourceFlow => e
         }
       }
       case SubAccess(expr, index, tpe)  => SubAccess(
-        remove_chirrtl_e(g)(expr), remove_chirrtl_e(MALE)(index), tpe)
+        remove_chirrtl_e(g)(expr), remove_chirrtl_e(SourceFlow)(index), tpe)
       case ex => ex map remove_chirrtl_e(g)
    }
    s match {
       case DefNode(info, name, value) =>
-        val valuex = remove_chirrtl_e(MALE)(value)
+        val valuex = remove_chirrtl_e(SourceFlow)(value)
         val sx = DefNode(info, name, valuex)
         // Check node is used for read port address
-        remove_chirrtl_e(FEMALE)(Reference(name, value.tpe))
+        remove_chirrtl_e(SinkFlow)(Reference(name, value.tpe))
         has_read_mport match {
           case None => sx
           case Some(en) => Block(Seq(sx, Connect(info, en, one)))
         }
       case Connect(info, loc, expr) =>
-        val rocx = remove_chirrtl_e(MALE)(expr)
-        val locx = remove_chirrtl_e(FEMALE)(loc)
+        val rocx = remove_chirrtl_e(SourceFlow)(expr)
+        val locx = remove_chirrtl_e(SinkFlow)(loc)
         val sx = Connect(info, locx, rocx)
         val stmts = ArrayBuffer[Statement]()
         has_read_mport match {
@@ -229,8 +229,8 @@ object RemoveCHIRRTL extends Transform {
         }
         if (stmts.isEmpty) sx else Block(sx +: stmts)
       case PartialConnect(info, loc, expr) =>
-        val locx = remove_chirrtl_e(FEMALE)(loc)
-        val rocx = remove_chirrtl_e(MALE)(expr)
+        val locx = remove_chirrtl_e(SinkFlow)(loc)
+        val rocx = remove_chirrtl_e(SourceFlow)(expr)
         val sx = PartialConnect(info, locx, rocx)
         val stmts = ArrayBuffer[Statement]()
         has_read_mport match {
@@ -247,7 +247,7 @@ object RemoveCHIRRTL extends Transform {
           }
         }
         if (stmts.isEmpty) sx else Block(sx +: stmts)
-      case sx => sx map remove_chirrtl_s(refs, raddrs) map remove_chirrtl_e(MALE)
+      case sx => sx map remove_chirrtl_s(refs, raddrs) map remove_chirrtl_e(SourceFlow)
     }
   }
 
diff --git a/src/main/scala/firrtl/passes/Resolves.scala b/src/main/scala/firrtl/passes/Resolves.scala
index e4a06525..53aac229 100644
--- a/src/main/scala/firrtl/passes/Resolves.scala
+++ b/src/main/scala/firrtl/passes/Resolves.scala
@@ -22,7 +22,7 @@ object ResolveKinds extends Pass {
       case sx: WDefInstance => kinds(sx.name) = InstanceKind
       case sx: DefMemory => kinds(sx.name) = MemKind
       case _ =>
-    } 
+    }
     s map find_stmt(kinds)
   }
 
@@ -40,14 +40,14 @@ object ResolveKinds extends Pass {
        map find_stmt(kinds)
        map resolve_stmt(kinds))
   }
- 
+
   def run(c: Circuit): Circuit =
     c copy (modules = c.modules map resolve_kinds)
 }
 
-object ResolveGenders extends Pass {
-  def resolve_e(g: Gender)(e: Expression): Expression = e match {
-    case ex: WRef => ex copy (gender = g)
+object ResolveFlows extends Pass {
+  def resolve_e(g: Flow)(e: Expression): Expression = e match {
+    case ex: WRef => ex copy (flow = g)
     case WSubField(exp, name, tpe, _) => WSubField(
       Utils.field_flip(exp.tpe, name) match {
         case Default => resolve_e(g)(exp)
@@ -56,25 +56,25 @@ object ResolveGenders extends Pass {
     case WSubIndex(exp, value, tpe, _) =>
       WSubIndex(resolve_e(g)(exp), value, tpe, g)
     case WSubAccess(exp, index, tpe, _) =>
-      WSubAccess(resolve_e(g)(exp), resolve_e(MALE)(index), tpe, g)
+      WSubAccess(resolve_e(g)(exp), resolve_e(SourceFlow)(index), tpe, g)
     case _ => e map resolve_e(g)
   }
-        
+
   def resolve_s(s: Statement): Statement = s match {
     //TODO(azidar): pretty sure don't need to do anything for Attach, but not positive...
     case IsInvalid(info, expr) =>
-      IsInvalid(info, resolve_e(FEMALE)(expr))
+      IsInvalid(info, resolve_e(SinkFlow)(expr))
     case Connect(info, loc, expr) =>
-      Connect(info, resolve_e(FEMALE)(loc), resolve_e(MALE)(expr))
+      Connect(info, resolve_e(SinkFlow)(loc), resolve_e(SourceFlow)(expr))
     case PartialConnect(info, loc, expr) =>
-      PartialConnect(info, resolve_e(FEMALE)(loc), resolve_e(MALE)(expr))
-    case sx => sx map resolve_e(MALE) map resolve_s
+      PartialConnect(info, resolve_e(SinkFlow)(loc), resolve_e(SourceFlow)(expr))
+    case sx => sx map resolve_e(SourceFlow) map resolve_s
   }
 
-  def resolve_gender(m: DefModule): DefModule = m map resolve_s
+  def resolve_flow(m: DefModule): DefModule = m map resolve_s
 
   def run(c: Circuit): Circuit =
-    c copy (modules = c.modules map resolve_gender)
+    c copy (modules = c.modules map resolve_flow)
 }
 
 object CInferMDir extends Pass {
@@ -111,7 +111,7 @@ object CInferMDir extends Pass {
     case e => e map infer_mdir_e(mports, dir)
   }
 
-  def infer_mdir_s(mports: MPortDirMap)(s: Statement): Statement = s match { 
+  def infer_mdir_s(mports: MPortDirMap)(s: Statement): Statement = s match {
     case sx: CDefMPort =>
        mports(sx.name) = sx.direction
        sx map infer_mdir_e(mports, MRead)
@@ -125,17 +125,17 @@ object CInferMDir extends Pass {
        sx
     case sx => sx map infer_mdir_s(mports) map infer_mdir_e(mports, MRead)
   }
-        
-  def set_mdir_s(mports: MPortDirMap)(s: Statement): Statement = s match { 
+
+  def set_mdir_s(mports: MPortDirMap)(s: Statement): Statement = s match {
     case sx: CDefMPort => sx copy (direction = mports(sx.name))
     case sx => sx map set_mdir_s(mports)
   }
-  
+
   def infer_mdir(m: DefModule): DefModule = {
     val mports = new MPortDirMap
     m map infer_mdir_s(mports) map set_mdir_s(mports)
   }
-     
+
   def run(c: Circuit): Circuit =
     c copy (modules = c.modules map infer_mdir)
 }
diff --git a/src/main/scala/firrtl/passes/SplitExpressions.scala b/src/main/scala/firrtl/passes/SplitExpressions.scala
index a32f5366..de955c9a 100644
--- a/src/main/scala/firrtl/passes/SplitExpressions.scala
+++ b/src/main/scala/firrtl/passes/SplitExpressions.scala
@@ -5,7 +5,7 @@ package passes
 
 import firrtl.ir._
 import firrtl.Mappers._
-import firrtl.Utils.{kind, gender, get_info}
+import firrtl.Utils.{kind, flow, get_info}
 
 // Datastructures
 import scala.collection.mutable
@@ -23,15 +23,15 @@ object SplitExpressions extends Pass {
           case e: DoPrim =>
             val name = namespace.newTemp
             v += DefNode(get_info(s), name, e)
-            WRef(name, e.tpe, kind(e), gender(e))
+            WRef(name, e.tpe, kind(e), flow(e))
           case e: Mux =>
             val name = namespace.newTemp
             v += DefNode(get_info(s), name, e)
-            WRef(name, e.tpe, kind(e), gender(e))
+            WRef(name, e.tpe, kind(e), flow(e))
           case e: ValidIf =>
             val name = namespace.newTemp
             v += DefNode(get_info(s), name, e)
-            WRef(name, e.tpe, kind(e), gender(e))
+            WRef(name, e.tpe, kind(e), flow(e))
           case _ => e
         }
 
diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala
index 52a2f95e..978ccc66 100644
--- a/src/main/scala/firrtl/passes/Uniquify.scala
+++ b/src/main/scala/firrtl/passes/Uniquify.scala
@@ -155,7 +155,7 @@ object Uniquify extends Transform {
       case e: WRef =>
         if (m.contains(e.name)) {
           val node = m(e.name)
-          (WRef(node.name, e.tpe, e.kind, e.gender), node.elts)
+          (WRef(node.name, e.tpe, e.kind, e.flow), node.elts)
         }
         else (e, Map())
       case e: WSubField =>
@@ -167,14 +167,14 @@ object Uniquify extends Transform {
           } else {
             (e.name, Map[String, NameMapNode]())
           }
-        (WSubField(subExp, retName, e.tpe, e.gender), retMap)
+        (WSubField(subExp, retName, e.tpe, e.flow), retMap)
       case e: WSubIndex =>
         val (subExp, subMap) = rec(e.expr, m)
-        (WSubIndex(subExp, e.value, e.tpe, e.gender), subMap)
+        (WSubIndex(subExp, e.value, e.tpe, e.flow), subMap)
       case e: WSubAccess =>
         val (subExp, subMap) = rec(e.expr, m)
         val index = uniquifyNamesExp(e.index, map)
-        (WSubAccess(subExp, index, e.tpe, e.gender), subMap)
+        (WSubAccess(subExp, index, e.tpe, e.flow), subMap)
       case (_: UIntLiteral | _: SIntLiteral) => (exp, m)
       case (_: Mux | _: ValidIf | _: DoPrim) =>
         (exp map ((e: Expression) => uniquifyNamesExp(e, map)), m)
@@ -265,7 +265,7 @@ object Uniquify extends Transform {
             if (nameMap.contains(sx.name)) {
               val node = nameMap(sx.name)
               val newType = uniquifyNamesType(sx.tpe, node.elts)
-              (Utils.create_exps(sx.name, sx.tpe) zip Utils.create_exps(node.name, newType)) foreach { 
+              (Utils.create_exps(sx.name, sx.tpe) zip Utils.create_exps(node.name, newType)) foreach {
                 case (from, to) => renames.rename(from.serialize, to.serialize)
               }
               DefWire(sx.info, node.name, newType)
@@ -382,4 +382,3 @@ object Uniquify extends Transform {
     CircuitState(result, outputForm, state.annotations, Some(renames))
   }
 }
-
diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala
index 330ca497..fdc81797 100644
--- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala
+++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala
@@ -47,11 +47,11 @@ object VerilogModulusCleanup extends Pass {
 
       def removeRem(e: Expression): Expression = e match {
         case e: DoPrim => e.op match {
-          case Rem => 
+          case Rem =>
             val name = namespace.newTemp
             val newType = e mapType verilogRemWidth(e)
             v += DefNode(get_info(s), name, e mapType verilogRemWidth(e))
-            val remRef = WRef(name, newType.tpe, kind(e), gender(e))
+            val remRef = WRef(name, newType.tpe, kind(e), flow(e))
             val remWidth = bitWidth(e.tpe)
             DoPrim(Bits, Seq(remRef), Seq(remWidth - 1, BigInt(0)), e.tpe)
           case _ => e
diff --git a/src/main/scala/firrtl/passes/ZeroWidth.scala b/src/main/scala/firrtl/passes/ZeroWidth.scala
index 6a79fe9a..83fc1b6b 100644
--- a/src/main/scala/firrtl/passes/ZeroWidth.scala
+++ b/src/main/scala/firrtl/passes/ZeroWidth.scala
@@ -63,14 +63,14 @@ object ZeroWidth extends Transform {
     }
     case BundleType(fields) =>
       if (fields.isEmpty) List(expr)
-      else fields.flatMap(f => findRemovable(WSubField(expr, f.name, f.tpe, MALE), f.tpe))
+      else fields.flatMap(f => findRemovable(WSubField(expr, f.name, f.tpe, SourceFlow), f.tpe))
     case VectorType(vtpe, size) =>
       if (size == 0) List(expr)
       else { // Only invoke findRemovable multiple times if a zero-width element is found
-        val es0 = findRemovable(WSubIndex(expr, 0, vtpe, MALE), vtpe)
+        val es0 = findRemovable(WSubIndex(expr, 0, vtpe, SourceFlow), vtpe)
         if (es0.isEmpty) es0
         else {
-          es0 ++ (1 until size).flatMap(i => findRemovable(WSubIndex(expr, i, vtpe, MALE), vtpe))
+          es0 ++ (1 until size).flatMap(i => findRemovable(WSubIndex(expr, i, vtpe, SourceFlow), vtpe))
         }
       }
   }
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
index f92a878e..b77629fc 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockListUtils.scala
@@ -20,8 +20,8 @@ object ClockListUtils {
     }
     val sourceList = moduleMap(lin.name) match {
       case ExtModule(i, n, ports, dn, p) =>
-        val portExps = ports.flatMap{p => create_exps(WRef(p.name, p.tpe, PortKind, to_gender(p.direction)))}
-        portExps.filter(e => (e.tpe == ClockType) && (gender(e) == FEMALE)).map(_.serialize)
+        val portExps = ports.flatMap{p => create_exps(WRef(p.name, p.tpe, PortKind, to_flow(p.direction)))}
+        portExps.filter(e => (e.tpe == ClockType) && (flow(e) == SinkFlow)).map(_.serialize)
       case _ => Nil
     }
     val sx = sourceList ++ s
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
index 44f45985..1e88a9b0 100644
--- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
@@ -160,7 +160,7 @@ class InferReadWrite extends Transform with SeqTransformBased with HasShellOptio
     CheckInitialization,
     InferTypes,
     ResolveKinds,
-    ResolveGenders
+    ResolveFlows
   )
   def execute(state: CircuitState): CircuitState = {
     val runTransform = state.annotations.contains(InferReadWriteAnnotation)
diff --git a/src/main/scala/firrtl/passes/memlib/MemUtils.scala b/src/main/scala/firrtl/passes/memlib/MemUtils.scala
index bf8b9401..b16a7424 100644
--- a/src/main/scala/firrtl/passes/memlib/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemUtils.scala
@@ -29,11 +29,11 @@ object toBitMask {
     (mask.tpe, dataType) match {
       case (mt: VectorType, dt: VectorType) =>
         seqCat((0 until mt.size).reverse map { i =>
-          hiermask(WSubIndex(mask, i, mt.tpe, UNKNOWNGENDER), dt.tpe)
+          hiermask(WSubIndex(mask, i, mt.tpe, UnknownFlow), dt.tpe)
         })
       case (mt: BundleType, dt: BundleType) =>
         seqCat((mt.fields zip dt.fields) map { case (mf, df) =>
-          hiermask(WSubField(mask, mf.name, mf.tpe, UNKNOWNGENDER), df.tpe)
+          hiermask(WSubField(mask, mf.name, mf.tpe, UnknownFlow), df.tpe)
         })
       case (UIntType(width), dt: GroundType) if width == IntWidth(BigInt(1)) =>
         seqCat(List.fill(bitWidth(dt).intValue)(mask))
@@ -80,9 +80,9 @@ object MemPortUtils {
   }
 
   def memPortField(s: DefMemory, p: String, f: String): Expression = {
-    val mem = WRef(s.name, memType(s), MemKind, UNKNOWNGENDER)
+    val mem = WRef(s.name, memType(s), MemKind, UnknownFlow)
     val t1 = field_type(mem.tpe, p)
     val t2 = field_type(t1, f)
-    WSubField(WSubField(mem, p, t1, UNKNOWNGENDER), f, t2, UNKNOWNGENDER)
+    WSubField(WSubField(mem, p, t1, UnknownFlow), f, t2, UnknownFlow)
   }
 }
diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
index 6ccfd601..f3ef917b 100644
--- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
+++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
@@ -126,7 +126,7 @@ class ReplSeqMem extends Transform with HasShellOptions {
         new SimpleMidTransform(InferTypes),
         Uniquify,
         new SimpleMidTransform(ResolveKinds),
-        new SimpleMidTransform(ResolveGenders))
+        new SimpleMidTransform(ResolveFlows))
 
   def execute(state: CircuitState): CircuitState = {
     val annos = state.annotations.collect { case a: ReplSeqMemAnnotation => a }
diff --git a/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala b/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala
index b552470d..41c47dce 100644
--- a/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala
+++ b/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala
@@ -38,14 +38,14 @@ object AnalysisUtils {
   /** Find a connection LHS's origin from a module's list of node-to-node connections
     *   regardless of whether constant propagation has been run.
     * Will search past trivial primop/mux's which do not affect its origin.
-    * Limitations: 
+    * Limitations:
     *   - Only works in a module (stops @ module inputs)
     *   - Only does trivial primop/mux's (is not complete)
     * TODO(shunshou): implement more equivalence cases (i.e. a + 0 = a)
     */
   def getOrigin(connects: Connects, s: String): Expression =
-    getOrigin(connects)(WRef(s, UnknownType, ExpKind, UNKNOWNGENDER))
-  def getOrigin(connects: Connects)(e: Expression): Expression = e match { 
+    getOrigin(connects)(WRef(s, UnknownType, ExpKind, UnknownFlow))
+  def getOrigin(connects: Connects)(e: Expression): Expression = e match {
     case Mux(cond, tv, fv, _) =>
       val fvOrigin = getOrigin(connects)(fv)
       val tvOrigin = getOrigin(connects)(tv)
@@ -58,12 +58,12 @@ object AnalysisUtils {
       else e
     case DoPrim(PrimOps.Or, args, consts, tpe) if args exists (weq(_, one)) => one
     case DoPrim(PrimOps.And, args, consts, tpe) if args exists (weq(_, zero)) => zero
-    case DoPrim(PrimOps.Bits, args, Seq(msb, lsb), tpe) =>  
+    case DoPrim(PrimOps.Bits, args, Seq(msb, lsb), tpe) =>
       val extractionWidth = (msb - lsb) + 1
       val nodeWidth = bitWidth(args.head.tpe)
       // if you're extracting the full bitwidth, then keep searching for origin
       if (nodeWidth == extractionWidth) getOrigin(connects)(args.head) else e
-    case DoPrim((PrimOps.AsUInt | PrimOps.AsSInt | PrimOps.AsClock), args, _, _) => 
+    case DoPrim((PrimOps.AsUInt | PrimOps.AsSInt | PrimOps.AsClock), args, _, _) =>
       getOrigin(connects)(args.head)
     // It is a correct optimization to treat ValidIf as a connection
     case ValidIf(cond, value, _) => getOrigin(connects)(value)
diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
index 10bcadfb..335e1121 100644
--- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
+++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
@@ -15,7 +15,7 @@ import collection.mutable
 
 /** This pass generates delay reigsters for memories for verilog */
 object VerilogMemDelays extends Pass {
-  val ug = UNKNOWNGENDER
+  val ug = UnknownFlow
   type Netlist = collection.mutable.HashMap[String, Expression]
   implicit def expToString(e: Expression): String = e.serialize
   private def NOT(e: Expression) = DoPrim(Not, Seq(e), Nil, BoolType)
@@ -58,14 +58,14 @@ object VerilogMemDelays extends Pass {
         // 1) reference to the last pipe register
         // 2) pipe registers and connects
         val node = DefNode(NoInfo, namespace.newTemp, netlist(e))
-        val wref = WRef(node.name, e.tpe, NodeKind, MALE)
+        val wref = WRef(node.name, e.tpe, NodeKind, SourceFlow)
         ((0 until n) foldLeft( (wref, Seq[Statement](node)) )){case ((ex, stmts), i) =>
           val name = namespace newName s"${LowerTypes.loweredName(e)}_pipe_$i"
           val exx = WRef(name, e.tpe, RegKind, ug)
           (exx, stmts ++ Seq(DefRegister(NoInfo, name, e.tpe, clk, zero, exx)) ++
             (if (i < n - 1 && WrappedExpression.weq(cond, one)) Seq(Connect(NoInfo, exx, ex)) else {
               val condn = namespace newName s"${LowerTypes.loweredName(e)}_en"
-              val condx = WRef(condn, BoolType, NodeKind, FEMALE)
+              val condx = WRef(condn, BoolType, NodeKind, SinkFlow)
               Seq(DefNode(NoInfo, condn, cond),
                   Connect(NoInfo, exx, Mux(condx, ex, exx, e.tpe)))
             })
@@ -94,7 +94,7 @@ object VerilogMemDelays extends Pass {
         Connect(NoInfo, memPortField(mem, writer, "addr"), addr),
         Connect(NoInfo, memPortField(mem, writer, "data"), data)
       )
- 
+
       stmts ++= ((sx.readers flatMap {reader =>
         // generate latency pipes for read ports (enable & addr)
         val clk = netlist(memPortField(sx, reader, "clk"))