diff options
| author | Jack Koenig | 2021-04-06 11:02:20 -0700 |
|---|---|---|
| committer | GitHub | 2021-04-06 18:02:20 +0000 |
| commit | 9a3dcf761e40b7ac36f9c867d0a36692d4d74c0c (patch) | |
| tree | 2d4314d384453aeef3375c180c2d769239977ebb /src/main/scala/firrtl/passes | |
| parent | ed5e03f960d89c8b5c999e030b2ae4586fa4a976 (diff) | |
Deprecate InlineCasts, add InlineAcrossCasts (#2146)
To maintain binary compatibility, InlineAcrossCasts is just aliases to
the now deprecated InlineCasts. We can make the binary incompatible
change of renaming the class and object for 1.5.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/main/scala/firrtl/passes')
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogModulusCleanup.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogPrep.scala | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala index baad2f4f..03dcf0a3 100644 --- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala +++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala @@ -32,7 +32,7 @@ object VerilogModulusCleanup extends Pass { Dependency[firrtl.transforms.FixAddingNegativeLiterals], Dependency[firrtl.transforms.ReplaceTruncatingArithmetic], Dependency[firrtl.transforms.InlineBitExtractionsTransform], - Dependency[firrtl.transforms.InlineCastsTransform], + Dependency[firrtl.transforms.InlineAcrossCastsTransform], Dependency[firrtl.transforms.LegalizeClocksTransform], Dependency[firrtl.transforms.FlattenRegUpdate] ) diff --git a/src/main/scala/firrtl/passes/VerilogPrep.scala b/src/main/scala/firrtl/passes/VerilogPrep.scala index ed5db92e..9499889a 100644 --- a/src/main/scala/firrtl/passes/VerilogPrep.scala +++ b/src/main/scala/firrtl/passes/VerilogPrep.scala @@ -28,7 +28,7 @@ object VerilogPrep extends Pass { Dependency[firrtl.transforms.FixAddingNegativeLiterals], Dependency[firrtl.transforms.ReplaceTruncatingArithmetic], Dependency[firrtl.transforms.InlineBitExtractionsTransform], - Dependency[firrtl.transforms.InlineCastsTransform], + Dependency[firrtl.transforms.InlineAcrossCastsTransform], Dependency[firrtl.transforms.LegalizeClocksTransform], Dependency[firrtl.transforms.FlattenRegUpdate], Dependency(passes.VerilogModulusCleanup), |
