Instance Annotations (#865)

Added Target, which now supports Instance Annotations. See #865 for details.

5 files changed, 20 insertions, 7 deletions

diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index f963e762..d6af69c1 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -128,11 +128,13 @@ class InlineInstances extends Transform {
         val port = ComponentName(s"$ref.$field", currentModule)
         val inst = ComponentName(s"$ref", currentModule)
         (renames.get(port), renames.get(inst)) match {
-          case (Some(p :: Nil), None)           => WRef(p.name, tpe, WireKind, gen)
+          case (Some(p :: Nil), _)              =>
+            p.toTarget match {
+              case ReferenceTarget(_, _, Seq(), r, Seq(TargetToken.Field(f))) => wsf.copy(expr = wr.copy(name = r), name = f)
+              case ReferenceTarget(_, _, Seq(), r, Seq()) => WRef(r, tpe, WireKind, gen)
+            }
           case (None,           Some(i :: Nil)) => wsf.map(appendRefPrefix(currentModule, renames))
           case (None,           None)           => wsf
-          case (Some(p),        Some(i))        => throw new PassException(
-            s"Inlining found multiple renames for ports ($p) and/or instances ($i). This should be impossible...")
         }
       case wr@ WRef(name, _, _, _) =>
         val comp = ComponentName(name, currentModule)
diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala
index 10d4e97f..73f967f4 100644
--- a/src/main/scala/firrtl/passes/Uniquify.scala
+++ b/src/main/scala/firrtl/passes/Uniquify.scala
@@ -36,7 +36,7 @@ object Uniquify extends Transform {
   def outputForm = UnknownForm
   private case class UniquifyException(msg: String) extends FIRRTLException(msg)
   private def error(msg: String)(implicit sinfo: Info, mname: String) =
-    throw new UniquifyException(s"$sinfo: [module $mname] $msg")
+    throw new UniquifyException(s"$sinfo: [moduleOpt $mname] $msg")
 
   // For creation of rename map
   private case class NameMapNode(name: String, elts: Map[String, NameMapNode])
@@ -45,7 +45,7 @@ object Uniquify extends Transform {
   // We don't add an _ in the collision check because elts could be Seq("")
   //   In this case, we're just really checking if prefix itself collides
   @tailrec
-  private [firrtl] def findValidPrefix(
+  def findValidPrefix(
       prefix: String,
       elts: Seq[String],
       namespace: collection.mutable.HashSet[String]): String = {
diff --git a/src/main/scala/firrtl/passes/VerilogRename.scala b/src/main/scala/firrtl/passes/VerilogRename.scala
new file mode 100644
index 00000000..4d51128c
--- /dev/null
+++ b/src/main/scala/firrtl/passes/VerilogRename.scala
@@ -0,0 +1,11 @@
+package firrtl.passes
+import firrtl.ir.Circuit
+import firrtl.transforms.VerilogRename
+
+@deprecated("Use transforms.VerilogRename, will be removed in 1.3", "1.2")
+object VerilogRename extends Pass {
+  override def run(c: Circuit): Circuit = new VerilogRename().run(c)
+  @deprecated("Use transforms.VerilogRename, will be removed in 1.3", "1.2")
+  def verilogRenameN(n: String): String =
+    if (firrtl.Utils.v_keywords(n)) "%s$".format(n) else n
+}
diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
index bb73beb4..6927075e 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
@@ -26,7 +26,7 @@ case class SinkAnnotation(target: Named, pin: String) extends
   def duplicate(n: Named) = this.copy(target = n)
 }
 
-/** Wires a Module's Source Component to one or more Sink
+/** Wires a Module's Source Target to one or more Sink
   * Modules/Components
   *
   * Sinks are wired to their closest source through their lowest
diff --git a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
index b89649d3..c5a7f21b 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
@@ -182,7 +182,7 @@ object WiringUtils {
       .collect { case (k, v) if sinkInsts.contains(k) => (k, v.flatten) }.toMap
   }
 
-  /** Helper script to extract a module name from a named Module or Component */
+  /** Helper script to extract a module name from a named Module or Target */
   def getModuleName(n: Named): String = {
     n match {
       case ModuleName(m, _)                   => m