API Cleanup - PrimOp & PrimOps

Add simple documentation
trait PrimOp -> abstract class PrimOp
Move PrimOp case objects to object PrimOps
Rename PrimOp case objects to match concrete syntax
Overrwrite toString for more canonical serialization
Update some PrimOps utility functions

4 files changed, 106 insertions, 106 deletions

diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 1a11c0a4..5a4f613c 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -90,45 +90,45 @@ object CheckHighForm extends Pass with LazyLogging {
     def checkHighFormPrimop(e: DoPrim) = {
       def correctNum(ne: Option[Int], nc: Int) = {
         ne match {
-          case Some(i) => if(e.args.length != i) errors.append(new IncorrectNumArgsException(e.op.getString, i))
+          case Some(i) => if(e.args.length != i) errors.append(new IncorrectNumArgsException(e.op.toString, i))
           case None => // Do Nothing
         }
-        if (e.consts.length != nc) errors.append(new IncorrectNumConstsException(e.op.getString, nc))
+        if (e.consts.length != nc) errors.append(new IncorrectNumConstsException(e.op.toString, nc))
       }
 
       e.op match {
-        case ADD_OP             => correctNum(Option(2),0)
-        case SUB_OP             => correctNum(Option(2),0)
-        case MUL_OP             => correctNum(Option(2),0)
-        case DIV_OP             => correctNum(Option(2),0)
-        case REM_OP             => correctNum(Option(2),0)
-        case LESS_OP            => correctNum(Option(2),0)
-        case LESS_EQ_OP         => correctNum(Option(2),0)
-        case GREATER_OP         => correctNum(Option(2),0)
-        case GREATER_EQ_OP      => correctNum(Option(2),0)
-        case EQUAL_OP           => correctNum(Option(2),0)
-        case NEQUAL_OP          => correctNum(Option(2),0)
-        case PAD_OP             => correctNum(Option(1),1)
-        case AS_UINT_OP         => correctNum(Option(1),0)
-        case AS_SINT_OP         => correctNum(Option(1),0)
-        case AS_CLOCK_OP        => correctNum(Option(1),0)
-        case SHIFT_LEFT_OP      => correctNum(Option(1),1)
-        case SHIFT_RIGHT_OP     => correctNum(Option(1),1)
-        case DYN_SHIFT_LEFT_OP  => correctNum(Option(2),0)
-        case DYN_SHIFT_RIGHT_OP => correctNum(Option(2),0)
-        case CONVERT_OP         => correctNum(Option(1),0)
-        case NEG_OP             => correctNum(Option(1),0)
-        case NOT_OP             => correctNum(Option(1),0)
-        case AND_OP             => correctNum(Option(2),0)
-        case OR_OP              => correctNum(Option(2),0)
-        case XOR_OP             => correctNum(Option(2),0)
-        case AND_REDUCE_OP      => correctNum(None,0)
-        case OR_REDUCE_OP       => correctNum(None,0)
-        case XOR_REDUCE_OP      => correctNum(None,0)
-        case CONCAT_OP          => correctNum(Option(2),0)
-        case BITS_SELECT_OP     => correctNum(Option(1),2)
-        case HEAD_OP            => correctNum(Option(1),1)
-        case TAIL_OP            => correctNum(Option(1),1)
+        case Add => correctNum(Option(2),0)
+        case Sub => correctNum(Option(2),0)
+        case Mul => correctNum(Option(2),0)
+        case Div => correctNum(Option(2),0)
+        case Rem => correctNum(Option(2),0)
+        case Lt => correctNum(Option(2),0)
+        case Leq => correctNum(Option(2),0)
+        case Gt => correctNum(Option(2),0)
+        case Geq => correctNum(Option(2),0)
+        case Eq => correctNum(Option(2),0)
+        case Neq => correctNum(Option(2),0)
+        case Pad => correctNum(Option(1),1)
+        case AsUInt => correctNum(Option(1),0)
+        case AsSInt => correctNum(Option(1),0)
+        case AsClock => correctNum(Option(1),0)
+        case Shl => correctNum(Option(1),1)
+        case Shr => correctNum(Option(1),1)
+        case Dshl => correctNum(Option(2),0)
+        case Dshr => correctNum(Option(2),0)
+        case Cvt => correctNum(Option(1),0)
+        case Neg => correctNum(Option(1),0)
+        case Not => correctNum(Option(1),0)
+        case And => correctNum(Option(2),0)
+        case Or => correctNum(Option(2),0)
+        case Xor => correctNum(Option(2),0)
+        case Andr => correctNum(None,0)
+        case Orr => correctNum(None,0)
+        case Xorr => correctNum(None,0)
+        case Cat => correctNum(Option(2),0)
+        case Bits => correctNum(Option(1),2)
+        case Head => correctNum(Option(1),1)
+        case Tail => correctNum(Option(1),1)
       }
     }
 
@@ -318,38 +318,38 @@ object CheckTypes extends Pass with LazyLogging {
       }
       
       e.op match {
-         case AS_UINT_OP =>  {}
-         case AS_SINT_OP =>  {}
-         case AS_CLOCK_OP =>  {}
-         case DYN_SHIFT_LEFT_OP =>  is_uint(e.args(1)); all_ground(e.args)
-         case DYN_SHIFT_RIGHT_OP => is_uint(e.args(1)); all_ground(e.args)
-         case ADD_OP =>  all_ground(e.args)
-         case SUB_OP =>  all_ground(e.args)
-         case MUL_OP =>  all_ground(e.args)
-         case DIV_OP =>  all_ground(e.args)
-         case REM_OP =>  all_ground(e.args)
-         case LESS_OP =>  all_ground(e.args)
-         case LESS_EQ_OP =>  all_ground(e.args)
-         case GREATER_OP =>  all_ground(e.args)
-         case GREATER_EQ_OP =>  all_ground(e.args)
-         case EQUAL_OP =>  all_ground(e.args)
-         case NEQUAL_OP =>  all_ground(e.args)
-         case PAD_OP =>  all_ground(e.args)
-         case SHIFT_LEFT_OP =>  all_ground(e.args)
-         case SHIFT_RIGHT_OP =>  all_ground(e.args)
-         case CONVERT_OP =>  all_ground(e.args)
-         case NEG_OP =>  all_ground(e.args)
-         case NOT_OP =>  all_ground(e.args)
-         case AND_OP =>  all_ground(e.args)
-         case OR_OP =>  all_ground(e.args)
-         case XOR_OP =>  all_ground(e.args)
-         case AND_REDUCE_OP =>  all_ground(e.args)
-         case OR_REDUCE_OP =>  all_ground(e.args)
-         case XOR_REDUCE_OP =>  all_ground(e.args)
-         case CONCAT_OP =>  all_ground(e.args)
-         case BITS_SELECT_OP =>  all_ground(e.args)
-         case HEAD_OP =>  all_ground(e.args)
-         case TAIL_OP =>  all_ground(e.args)
+         case AsUInt =>
+         case AsSInt =>
+         case AsClock =>
+         case Dshl => is_uint(e.args(1)); all_ground(e.args)
+         case Dshr => is_uint(e.args(1)); all_ground(e.args)
+         case Add => all_ground(e.args)
+         case Sub => all_ground(e.args)
+         case Mul => all_ground(e.args)
+         case Div => all_ground(e.args)
+         case Rem => all_ground(e.args)
+         case Lt => all_ground(e.args)
+         case Leq => all_ground(e.args)
+         case Gt => all_ground(e.args)
+         case Geq => all_ground(e.args)
+         case Eq => all_ground(e.args)
+         case Neq => all_ground(e.args)
+         case Pad => all_ground(e.args)
+         case Shl => all_ground(e.args)
+         case Shr => all_ground(e.args)
+         case Cvt => all_ground(e.args)
+         case Neg => all_ground(e.args)
+         case Not => all_ground(e.args)
+         case And => all_ground(e.args)
+         case Or => all_ground(e.args)
+         case Xor => all_ground(e.args)
+         case Andr => all_ground(e.args)
+         case Orr => all_ground(e.args)
+         case Xorr => all_ground(e.args)
+         case Cat => all_ground(e.args)
+         case Bits => all_ground(e.args)
+         case Head => all_ground(e.args)
+         case Tail => all_ground(e.args)
       }
    }
       
diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala
index e562f71d..f8fd5654 100644
--- a/src/main/scala/firrtl/passes/ConstProp.scala
+++ b/src/main/scala/firrtl/passes/ConstProp.scala
@@ -30,6 +30,7 @@ package firrtl.passes
 import firrtl._
 import firrtl.Utils._
 import firrtl.Mappers._
+import firrtl.PrimOps._
 
 import annotation.tailrec
 
@@ -137,10 +138,10 @@ object ConstProp extends Pass {
           case _ => false
         }
       x match {
-        case DoPrim(LESS_OP,      Seq(a,b),_,_) if(isUInt(a) && isZero(b)) => zero
-        case DoPrim(LESS_EQ_OP,   Seq(a,b),_,_) if(isZero(a) && isUInt(b)) => one
-        case DoPrim(GREATER_OP,   Seq(a,b),_,_) if(isZero(a) && isUInt(b)) => zero
-        case DoPrim(GREATER_EQ_OP,Seq(a,b),_,_) if(isUInt(a) && isZero(b)) => one
+        case DoPrim(Lt,  Seq(a,b),_,_) if(isUInt(a) && isZero(b)) => zero
+        case DoPrim(Leq, Seq(a,b),_,_) if(isZero(a) && isUInt(b)) => one
+        case DoPrim(Gt,  Seq(a,b),_,_) if(isZero(a) && isUInt(b)) => zero
+        case DoPrim(Geq, Seq(a,b),_,_) if(isUInt(a) && isZero(b)) => one
         case e => e
       }
     }
@@ -179,15 +180,15 @@ object ConstProp extends Pass {
           def r1 = range(e.args(1))
           e.op match {
             // Always true
-            case LESS_OP       if (r0 < r1) => one
-            case LESS_EQ_OP    if (r0 <= r1) => one
-            case GREATER_OP    if (r0 > r1) => one
-            case GREATER_EQ_OP if (r0 >= r1) => one
+            case Lt  if (r0 < r1) => one
+            case Leq if (r0 <= r1) => one
+            case Gt  if (r0 > r1) => one
+            case Geq if (r0 >= r1) => one
             // Always false
-            case LESS_OP       if (r0 >= r1) => zero
-            case LESS_EQ_OP    if (r0 > r1) => zero
-            case GREATER_OP    if (r0 <= r1) => zero
-            case GREATER_EQ_OP if (r0 < r1) => zero
+            case Lt  if (r0 >= r1) => zero
+            case Leq if (r0 > r1) => zero
+            case Gt  if (r0 <= r1) => zero
+            case Geq if (r0 < r1) => zero
             case _ => e
           }
         }
@@ -198,20 +199,20 @@ object ConstProp extends Pass {
   }
 
   private def constPropPrim(e: DoPrim): Expression = e.op match {
-    case SHIFT_LEFT_OP => foldShiftLeft(e)
-    case SHIFT_RIGHT_OP => foldShiftRight(e)
-    case CONCAT_OP => foldConcat(e)
-    case AND_OP => FoldAND(e)
-    case OR_OP => FoldOR(e)
-    case XOR_OP => FoldXOR(e)
-    case EQUAL_OP => FoldEqual(e)
-    case NEQUAL_OP => FoldNotEqual(e)
-    case LESS_OP|LESS_EQ_OP|GREATER_OP|GREATER_EQ_OP => foldComparison(e)
-    case NOT_OP => e.args(0) match {
+    case Shl => foldShiftLeft(e)
+    case Shr => foldShiftRight(e)
+    case Cat => foldConcat(e)
+    case And => FoldAND(e)
+    case Or => FoldOR(e)
+    case Xor => FoldXOR(e)
+    case Eq => FoldEqual(e)
+    case Neq => FoldNotEqual(e)
+    case (Lt | Leq | Gt | Geq) => foldComparison(e)
+    case Not => e.args(0) match {
       case UIntLiteral(v, IntWidth(w)) => UIntLiteral(v ^ ((BigInt(1) << w.toInt) - 1), IntWidth(w))
       case _ => e
     }
-    case BITS_SELECT_OP => e.args(0) match {
+    case Bits => e.args(0) match {
       case UIntLiteral(v, _) => {
         val hi = e.consts(0).toInt
         val lo = e.consts(1).toInt
@@ -220,7 +221,7 @@ object ConstProp extends Pass {
       }
       case x if long_BANG(tpe(e)) == long_BANG(tpe(x)) => tpe(x) match {
         case t: UIntType => x
-        case _ => DoPrim(AS_UINT_OP, Seq(x), Seq(), tpe(e))
+        case _ => DoPrim(AsUInt, Seq(x), Seq(), tpe(e))
       }
       case _ => e
     }
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala
index 3054aab0..0d269a98 100644
--- a/src/main/scala/firrtl/passes/PadWidths.scala
+++ b/src/main/scala/firrtl/passes/PadWidths.scala
@@ -3,6 +3,7 @@ package passes
 
 import firrtl.Mappers.{ExpMap, StmtMap}
 import firrtl.Utils.{tpe, long_BANG}
+import firrtl.PrimOps._
 
 // Makes all implicit width extensions and truncations explicit
 object PadWidths extends Pass {
@@ -17,17 +18,15 @@ object PadWidths extends Pass {
          // default case should never be reached
       }
       if (i > width(e))
-         DoPrim(PAD_OP, Seq(e), Seq(i), tx)
+         DoPrim(Pad, Seq(e), Seq(i), tx)
       else if (i < width(e))
-         DoPrim(BITS_SELECT_OP, Seq(e), Seq(i - 1, 0), tx)
+         DoPrim(Bits, Seq(e), Seq(i - 1, 0), tx)
       else e
    }
    // Recursive, updates expression so children exp's have correct widths
    private def onExp(e: Expression): Expression = {
-      val sensitiveOps = Seq(
-         LESS_OP, LESS_EQ_OP, GREATER_OP, GREATER_EQ_OP, EQUAL_OP,
-         NEQUAL_OP, NOT_OP, AND_OP, OR_OP, XOR_OP, ADD_OP, SUB_OP,
-         MUL_OP, DIV_OP, REM_OP, SHIFT_RIGHT_OP)
+      val sensitiveOps = Seq( Lt, Leq, Gt, Geq, Eq, Neq, Not, And, Or, Xor,
+        Add, Sub, Mul, Div, Rem, Shr)
       val x = e map onExp
       x match {
          case Mux(cond, tval, fval, tpe) => {
@@ -40,15 +39,15 @@ object PadWidths extends Pass {
                val i = args.map(a => width(a)).foldLeft(0) {(a, b) => math.max(a, b)}
                x map fixup(i)
             }
-            case DYN_SHIFT_LEFT_OP => {
+            case Dshl => {
                // special case as args aren't all same width
                val ax = fixup(width(tpe))(args(0))
-               DoPrim(DSHLW_OP, Seq(ax, args(1)), consts, tpe)
+               DoPrim(Dshlw, Seq(ax, args(1)), consts, tpe)
             }
-            case SHIFT_LEFT_OP => {
+            case Shl => {
                // special case as arg should be same width as result
                val ax = fixup(width(tpe))(args(0))
-               DoPrim(SHLW_OP, Seq(ax), consts, tpe)
+               DoPrim(Shlw, Seq(ax), consts, tpe)
             }
             case _ => x
          }
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index ce1c7eed..739d0c2f 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -894,7 +894,7 @@ object RemoveAccesses extends Pass {
 object Legalize extends Pass {
   def name = "Legalize"
   def legalizeShiftRight (e: DoPrim): Expression = e.op match {
-    case SHIFT_RIGHT_OP => {
+    case Shr => {
       val amount = e.consts(0).toInt
       val width = long_BANG(tpe(e.args(0)))
       lazy val msb = width - 1
@@ -902,7 +902,7 @@ object Legalize extends Pass {
         e.tpe match {
           case t: UIntType => UIntLiteral(0, IntWidth(1))
           case t: SIntType =>
-            DoPrim(BITS_SELECT_OP, e.args, Seq(msb, msb), SIntType(IntWidth(1)))
+            DoPrim(Bits, e.args, Seq(msb, msb), SIntType(IntWidth(1)))
           case t => error(s"Unsupported type ${t} for Primop Shift Right")
         }
       } else {
@@ -920,7 +920,7 @@ object Legalize extends Pass {
         case _: UIntType => UIntType(IntWidth(w))
         case _: SIntType => SIntType(IntWidth(w))
       }
-      Connect(c.info, c.loc, DoPrim(BITS_SELECT_OP, Seq(c.expr), Seq(w-1, 0), newType))
+      Connect(c.info, c.loc, DoPrim(Bits, Seq(c.expr), Seq(w-1, 0), newType))
     }
   }
   def run (c: Circuit): Circuit = {
@@ -949,11 +949,11 @@ object VerilogWrap extends Pass {
       e map (v_wrap_e) match {
          case (e:DoPrim) => {
             def a0 () = e.args(0)
-            if (e.op == TAIL_OP) {
+            if (e.op == Tail) {
                (a0()) match {
                   case (e0:DoPrim) => {
-                     if (e0.op == ADD_OP) DoPrim(ADDW_OP,e0.args,Seq(),tpe(e))
-                     else if (e0.op == SUB_OP) DoPrim(SUBW_OP,e0.args,Seq(),tpe(e))
+                     if (e0.op == Add) DoPrim(Addw,e0.args,Seq(),tpe(e))
+                     else if (e0.op == Sub) DoPrim(Subw,e0.args,Seq(),tpe(e))
                      else e
                   }
                   case (e0) => e