diff options
| author | Donggyu | 2016-09-07 16:55:56 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-07 16:55:56 -0700 |
| commit | 296a65ebb895d100c3cbde6df7c0303d6942e5d5 (patch) | |
| tree | 09f8365353992e4de46c2b660bdeb737a26981b8 /src/main/scala/firrtl/passes | |
| parent | a404cf5b2c4ca6457c964eb32aae8330c48422e1 (diff) | |
| parent | ef6068fd0bd79b7e30602687caa480461d1b629d (diff) | |
Merge pull request #276 from ucb-bar/cleanup_miscs
Clean up WIR, PrimOps
Diffstat (limited to 'src/main/scala/firrtl/passes')
| -rw-r--r-- | src/main/scala/firrtl/passes/ConstProp.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/Inline.scala | 6 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveEmpty.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/ReplaceSubAccess.scala | 7 |
4 files changed, 4 insertions, 13 deletions
diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala index 2e8b53f3..a4d9078c 100644 --- a/src/main/scala/firrtl/passes/ConstProp.scala +++ b/src/main/scala/firrtl/passes/ConstProp.scala @@ -234,7 +234,7 @@ object ConstProp extends Pass { val hi = e.consts(0).toInt val lo = e.consts(1).toInt require(hi >= lo) - UIntLiteral((lit.value >> lo) & ((BigInt(1) << (hi - lo + 1)) - 1), widthBANG(e.tpe)) + UIntLiteral((lit.value >> lo) & ((BigInt(1) << (hi - lo + 1)) - 1), width_BANG(e.tpe)) } case x if long_BANG(e.tpe) == long_BANG(x.tpe) => x.tpe match { case t: UIntType => x diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala index a8fda1bf..c4529bd9 100644 --- a/src/main/scala/firrtl/passes/Inline.scala +++ b/src/main/scala/firrtl/passes/Inline.scala @@ -4,11 +4,9 @@ package passes // Datastructures import scala.collection.mutable -import firrtl.Mappers.{ExpMap,StmtMap} import firrtl.ir._ -import firrtl.passes.{PassException,PassExceptions} -import Annotations.{Loose, Unstable, Annotation, TransID, Named, ModuleName, ComponentName, CircuitName, AnnotationMap} - +import firrtl.Annotations._ +import firrtl.Mappers.{ExpMap, StmtMap} // Tags an annotation to be consumed by this pass case class InlineAnnotation(target: Named, tID: TransID) extends Annotation with Loose with Unstable { diff --git a/src/main/scala/firrtl/passes/RemoveEmpty.scala b/src/main/scala/firrtl/passes/RemoveEmpty.scala index e765d1f4..7ba2ef09 100644 --- a/src/main/scala/firrtl/passes/RemoveEmpty.scala +++ b/src/main/scala/firrtl/passes/RemoveEmpty.scala @@ -15,5 +15,3 @@ object RemoveEmpty extends Pass { } def run(c: Circuit): Circuit = Circuit(c.info, c.modules.map(onModule _), c.main) } - -// vim: set ts=4 sw=4 et: diff --git a/src/main/scala/firrtl/passes/ReplaceSubAccess.scala b/src/main/scala/firrtl/passes/ReplaceSubAccess.scala index 8e911a96..ce95be13 100644 --- a/src/main/scala/firrtl/passes/ReplaceSubAccess.scala +++ b/src/main/scala/firrtl/passes/ReplaceSubAccess.scala @@ -22,11 +22,6 @@ object ReplaceAccesses extends Pass { case e => e map onExp } - val newModules = c.modules map { - case m: ExtModule => m - case Module(i, n, ps, b) => Module(i, n, ps, onStmt(b)) - } - - Circuit(c.info, newModules, c.main) + c copy (modules = c.modules map (_ map onStmt)) } } |
