diff options
| author | Andrew Waterman | 2019-01-23 13:27:19 -0800 |
|---|---|---|
| committer | Adam Izraelevitz | 2019-01-23 13:27:19 -0800 |
| commit | 1738c1ef0ac95fae25d52586b3b0348de80de2ff (patch) | |
| tree | e28d770a8ad05b7f9635365248ee6a44a766714e /src/main/scala/firrtl/passes | |
| parent | df3c3fb5eedd3e2ac95b9f210268e4e515d6344c (diff) | |
Improve Shl codegen; eliminate Shlw WIR node (#994)
* Improve Shl codegen; eliminate Shlw WIR node
If we emit shl(x, k) as {x, k'h0} instead of (x << k), then there's
no need for Verilog-specific padding in the PadWidths pass. Avoiding
the redundant padding improves compiler/simulator performance and
renders Shlw unnecessary.
* [skip formal checks] Add test
Diffstat (limited to 'src/main/scala/firrtl/passes')
| -rw-r--r-- | src/main/scala/firrtl/passes/PadWidths.scala | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala index c9aa1539..cbd8250a 100644 --- a/src/main/scala/firrtl/passes/PadWidths.scala +++ b/src/main/scala/firrtl/passes/PadWidths.scala @@ -44,9 +44,6 @@ object PadWidths extends Pass { case Dshl => // special case as args aren't all same width ex copy (op = Dshlw, args = Seq(fixup(width(ex.tpe))(ex.args.head), ex.args(1))) - case Shl => - // special case as arg should be same width as result - ex copy (op = Shlw, args = Seq(fixup(width(ex.tpe))(ex.args.head))) case _ => ex } case ex => ex |