diff options
| author | Jack Koenig | 2021-01-19 20:19:08 -0800 |
|---|---|---|
| committer | GitHub | 2021-01-20 04:19:08 +0000 |
| commit | 031fe1382660867750e6eeebea5665c137dbccbe (patch) | |
| tree | cc65ca17a57fe093a73a5c25059f42cd22332a76 /src/main/scala/firrtl/passes | |
| parent | 698a9dca52f819aca6309e3b03f2420a71bc89a6 (diff) | |
Cleanup some warnings (#2032)
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/main/scala/firrtl/passes')
5 files changed, 3 insertions, 10 deletions
diff --git a/src/main/scala/firrtl/passes/CInferMDir.scala b/src/main/scala/firrtl/passes/CInferMDir.scala index 90f1c739..cca8fde4 100644 --- a/src/main/scala/firrtl/passes/CInferMDir.scala +++ b/src/main/scala/firrtl/passes/CInferMDir.scala @@ -22,22 +22,19 @@ object CInferMDir extends Pass { case None => case Some(p) => mports(e.name) = (p, dir) match { - case (MInfer, MInfer) => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir") case (MInfer, MWrite) => MWrite case (MInfer, MRead) => MRead case (MInfer, MReadWrite) => MReadWrite - case (MWrite, MInfer) => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir") case (MWrite, MWrite) => MWrite case (MWrite, MRead) => MReadWrite case (MWrite, MReadWrite) => MReadWrite - case (MRead, MInfer) => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir") case (MRead, MWrite) => MReadWrite case (MRead, MRead) => MRead case (MRead, MReadWrite) => MReadWrite - case (MReadWrite, MInfer) => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir") case (MReadWrite, MWrite) => MReadWrite case (MReadWrite, MRead) => MReadWrite case (MReadWrite, MReadWrite) => MReadWrite + case _ => throwInternalError(s"infer_mdir_e: shouldn't be here - $p, $dir") } } e diff --git a/src/main/scala/firrtl/passes/CheckHighForm.scala b/src/main/scala/firrtl/passes/CheckHighForm.scala index 5514741a..7e305b33 100644 --- a/src/main/scala/firrtl/passes/CheckHighForm.scala +++ b/src/main/scala/firrtl/passes/CheckHighForm.scala @@ -243,8 +243,7 @@ trait CheckHighFormLike { this: Pass => errors.append(new NegUIntException(info, mname)) case ex: DoPrim => checkHighFormPrimop(info, mname, ex) case _: Reference | _: WRef | _: UIntLiteral | _: Mux | _: ValidIf => - case ex: SubAccess => validSubexp(info, mname)(ex.expr) - case ex: WSubAccess => validSubexp(info, mname)(ex.expr) + case ex: SubAccess => validSubexp(info, mname)(ex.expr) case ex => ex.foreach(validSubexp(info, mname)) } e.foreach(checkHighFormW(info, mname + "/" + e.serialize)) @@ -284,7 +283,6 @@ trait CheckHighFormLike { this: Pass => if (sx.depth <= 0) errors.append(new NegMemSizeException(info, mname)) case sx: DefInstance => checkInstance(info, mname, sx.module) - case sx: WDefInstance => checkInstance(info, mname, sx.module) case sx: Connect => checkValidLoc(info, mname, sx.loc) case sx: PartialConnect => checkValidLoc(info, mname, sx.loc) case sx: Print => checkFstring(info, mname, sx.string, sx.args.length) diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala index aa2095fa..56cd4dd2 100644 --- a/src/main/scala/firrtl/passes/InferWidths.scala +++ b/src/main/scala/firrtl/passes/InferWidths.scala @@ -110,6 +110,7 @@ class InferWidths extends Transform with ResolvedAnnotationPaths with Dependency case (AsyncResetType, AsyncResetType) => Nil case (ResetType, _) => Nil case (_, ResetType) => Nil + case _ => throwInternalError("Shouldn't be here") } private def addExpConstraints(e: Expression)(implicit constraintSolver: ConstraintSolver): Expression = diff --git a/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala b/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala index 9ad653cf..671a08b9 100644 --- a/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala +++ b/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala @@ -16,7 +16,6 @@ object RemoveAllButClocks extends Pass { case DefWire(i, n, ClockType) => s case DefNode(i, n, value) if value.tpe == ClockType => s case Connect(i, l, r) if l.tpe == ClockType => s - case sx: WDefInstance => sx case sx: DefInstance => sx case sx: Block => sx case sx: Conditionally => sx diff --git a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala index d926f6a9..cab6aa5f 100644 --- a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala +++ b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala @@ -90,8 +90,6 @@ object WiringUtils { def getChildrenMap(c: Circuit): ChildrenMap = { val childrenMap = new ChildrenMap() def getChildren(mname: String)(s: Statement): Unit = s match { - case s: WDefInstance => - childrenMap(mname) = childrenMap(mname) :+ ((s.name, s.module)) case s: DefInstance => childrenMap(mname) = childrenMap(mname) :+ ((s.name, s.module)) case s => s.foreach(getChildren(mname)) |