diff options
| author | Adam Izraelevitz | 2017-12-27 16:02:29 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-12-27 16:02:29 -0800 |
| commit | ef61bb94879305a8259daeb6c67f72428bc5d5a4 (patch) | |
| tree | 50d077e0f41d9b2d42bda2a5c2fe7223f81a3acb /src/main/scala/firrtl/passes | |
| parent | 339548ee598d0e3e593dff9db31783db99004035 (diff) | |
Removed top preamble (#640)
Diffstat (limited to 'src/main/scala/firrtl/passes')
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveValidIf.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala index 06f0874a..68d16c30 100644 --- a/src/main/scala/firrtl/passes/RemoveValidIf.scala +++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala @@ -30,7 +30,7 @@ object RemoveValidIf extends Pass { // Recursive. Replaces IsInvalid with connecting zero private def onStmt(s: Statement): Statement = s map onStmt map onExp match { case invalid @ IsInvalid(info, loc) => loc.tpe match { - case _: AnalogType => invalid // Unclear what we should do, can't remove or we emit invalid Firrtl + case _: AnalogType => EmptyStmt case tpe => Connect(info, loc, getGroundZero(tpe)) } // Register connected to itself (since reset has been made explicit) is a register with no reset |