diff options
| author | Colin Schmidt | 2016-10-30 14:18:48 -0700 |
|---|---|---|
| committer | Donggyu | 2016-10-30 14:18:48 -0700 |
| commit | be87c1e2481d14a2e0b68668fbfd901d3416dddd (patch) | |
| tree | c1febd7d69a3079e5459de4d62ed3f1e7f80c470 /src/main/scala/firrtl/passes | |
| parent | 5b35f2d2722f72c81d2d6c507cd379be2a1476d8 (diff) | |
Keep package name + directory structure consistent (#354)
* Keep package name + directory structure consistent
This annoyed me so heres a PR
* fix InferReadWrite references
* delete .ConvertFixedToSInt.scala.swo
Diffstat (limited to 'src/main/scala/firrtl/passes')
| -rw-r--r-- | src/main/scala/firrtl/passes/.ConvertFixedToSInt.scala.swo | bin | 20480 -> 0 bytes | |||
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/InferReadWrite.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala | 1 |
3 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/.ConvertFixedToSInt.scala.swo b/src/main/scala/firrtl/passes/.ConvertFixedToSInt.scala.swo Binary files differdeleted file mode 100644 index abd7c349..00000000 --- a/src/main/scala/firrtl/passes/.ConvertFixedToSInt.scala.swo +++ /dev/null diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index ffdea1f2..28291135 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -26,6 +26,7 @@ MODIFICATIONS. */ package firrtl.passes +package memlib import firrtl._ import firrtl.ir._ diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala index 2f7126b4..3aa63942 100644 --- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala +++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala @@ -26,6 +26,7 @@ MODIFICATIONS. */ package firrtl.passes +package memlib import firrtl._ import firrtl.ir._ |