diff options
| author | Albert Magyar | 2020-04-13 14:01:35 -0700 |
|---|---|---|
| committer | Albert Magyar | 2020-04-13 17:48:00 -0700 |
| commit | 66c3695550f60903efe90bb6839d0f75cad4d7fd (patch) | |
| tree | cb56c8bc801403ba17964b2d8024624dec71abe4 /src/main/scala/firrtl/passes | |
| parent | bda5a61ad6abc965b21f390b47f0e9b1002eea02 (diff) | |
Ensure PadWidths is run in mverilog compiler
Diffstat (limited to 'src/main/scala/firrtl/passes')
| -rw-r--r-- | src/main/scala/firrtl/passes/PadWidths.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala index 0b318511..163b2270 100644 --- a/src/main/scala/firrtl/passes/PadWidths.scala +++ b/src/main/scala/firrtl/passes/PadWidths.scala @@ -17,8 +17,9 @@ object PadWidths extends Pass { ((new mutable.LinkedHashSet()) ++ firrtl.stage.Forms.LowForm - Dependency(firrtl.passes.Legalize) - + Dependency(firrtl.passes.RemoveValidIf) - + Dependency[firrtl.transforms.ConstantPropagation]).toSeq + + Dependency(firrtl.passes.RemoveValidIf)).toSeq + + override val optionalPrerequisites = Seq(Dependency[firrtl.transforms.ConstantPropagation]) override val dependents = Seq( Dependency(firrtl.passes.memlib.VerilogMemDelays), |