remove unnecessary parentheses

17 files changed, 67 insertions, 67 deletions

diff --git a/src/main/scala/firrtl/passes/AnnotateMemMacros.scala b/src/main/scala/firrtl/passes/AnnotateMemMacros.scala
index aa5acb12..bfc13e46 100644
--- a/src/main/scala/firrtl/passes/AnnotateMemMacros.scala
+++ b/src/main/scala/firrtl/passes/AnnotateMemMacros.scala
@@ -137,7 +137,7 @@ object AnnotateMemMacros extends Pass {
 
   def annotateModMems(m: DefModule) = m map updateStmts(getConnects(m))
 
-  def run(c: Circuit) = c copy (modules = (c.modules map annotateModMems))
+  def run(c: Circuit) = c copy (modules = c.modules map annotateModMems)
 }
 
 // TODO: Add floorplan info?
diff --git a/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala b/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
index d229aaf3..e77955ed 100644
--- a/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
+++ b/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
@@ -193,7 +193,7 @@ case class SRAMCompiler(
     val squarestAspectRatio = validMinConfigsSquareness.unzip._1.min
     val validConfig = validMinConfigsSquareness(squarestAspectRatio)
     val validRules = defaultSearchOrdering filter (r =>
-      (validConfig.width <= r.getValidWidths.max && validConfig.depth <= r.getValidDepths.max))
+      validConfig.width <= r.getValidWidths.max && validConfig.depth <= r.getValidDepths.max)
     // TODO: don't just take first option
     // TODO: More optimal split if particular value is in range but not supported
     // TODO: Support up to 2 read ports, 2 write ports; should be power of 2?
@@ -271,7 +271,7 @@ class AnnotateValidMemConfigs(reader: Option[YamlFileReader]) extends Pass {
   def updateStmts(s: Statement): Statement = s match {
     case m: DefMemory if containsInfo(m.info, "useMacro") => sramCompilers match {
       case None => m
-      case Some(compiler) if (m.readwriters.length == 1) =>
+      case Some(compiler) if m.readwriters.length == 1 =>
         compiler.sp match {
           case None => error("Design needs RW port memory compiler!")
           case Some(p) => p append m
@@ -285,5 +285,5 @@ class AnnotateValidMemConfigs(reader: Option[YamlFileReader]) extends Pass {
     case s => s map updateStmts
   }
 
-  def run(c: Circuit) = c copy (modules = (c.modules map (_ map updateStmts)))
+  def run(c: Circuit) = c copy (modules = c.modules map (_ map updateStmts))
 }
diff --git a/src/main/scala/firrtl/passes/CheckChirrtl.scala b/src/main/scala/firrtl/passes/CheckChirrtl.scala
index 9858c0d2..36285bf1 100644
--- a/src/main/scala/firrtl/passes/CheckChirrtl.scala
+++ b/src/main/scala/firrtl/passes/CheckChirrtl.scala
@@ -109,14 +109,14 @@ object CheckChirrtl extends Pass {
 
     def checkName(info: Info, mname: String, names: NameSet)(name: String): String = {
       if (names(name))
-        errors append (new NotUniqueException(info, mname, name))
+        errors append new NotUniqueException(info, mname, name)
       names += name
       name 
     }
 
     def checkChirrtlS(minfo: Info, mname: String, names: NameSet)(s: Statement): Statement = {
       val info = get_info(s) match {case NoInfo => minfo case x => x}
-      (s map checkName(info, mname, names)) match {
+      s map checkName(info, mname, names) match {
         case s: DefMemory =>
           if (hasFlip(s.dataType)) errors append new MemWithFlipException(info, mname, s.name)
           if (s.depth <= 0) errors append new NegMemSizeException(info, mname)
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 75b9a01d..2e7f4ff6 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -87,7 +87,7 @@ object CheckHighForm extends Pass {
       def correctNum(ne: Option[Int], nc: Int) {
         ne match {
           case Some(i) if e.args.length != i =>
-            errors append (new IncorrectNumArgsException(info, mname, e.op.toString, i))
+            errors append new IncorrectNumArgsException(info, mname, e.op.toString, i)
           case _ => // Do Nothing
         }
         if (e.consts.length != nc)
@@ -181,7 +181,7 @@ object CheckHighForm extends Pass {
 
     def checkHighFormS(minfo: Info, mname: String, names: NameSet)(s: Statement): Statement = {
       val info = get_info(s) match {case NoInfo => minfo case x => x}
-      (s map checkName(info, mname, names)) match {
+      s map checkName(info, mname, names) match {
         case s: DefMemory =>
           if (hasFlip(s.dataType))
             errors append new MemWithFlipException(info, mname, s.name)
@@ -342,9 +342,9 @@ object CheckTypes extends Pass {
         case (e: WSubIndex) => e.exp.tpe match {
           case (t: VectorType) if e.value < t.size =>
           case (t: VectorType) =>
-            errors append (new IndexTooLarge(info, mname, e.value))
+            errors append new IndexTooLarge(info, mname, e.value)
           case _ =>
-            errors append (new IndexOnNonVector(info, mname))
+            errors append new IndexOnNonVector(info, mname)
         }
         case (e: WSubAccess) =>
           e.exp.tpe match {
diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala
index a95d3de0..cf32092c 100644
--- a/src/main/scala/firrtl/passes/ConstProp.scala
+++ b/src/main/scala/firrtl/passes/ConstProp.scala
@@ -139,10 +139,10 @@ object ConstProp extends Pass {
           case _ => false
         }
       x match {
-        case DoPrim(Lt,  Seq(a,b),_,_) if(isUInt(a) && isZero(b)) => zero
-        case DoPrim(Leq, Seq(a,b),_,_) if(isZero(a) && isUInt(b)) => one
-        case DoPrim(Gt,  Seq(a,b),_,_) if(isZero(a) && isUInt(b)) => zero
-        case DoPrim(Geq, Seq(a,b),_,_) if(isUInt(a) && isZero(b)) => one
+        case DoPrim(Lt,  Seq(a,b),_,_) if isUInt(a) && isZero(b) => zero
+        case DoPrim(Leq, Seq(a,b),_,_) if isZero(a) && isUInt(b) => one
+        case DoPrim(Gt,  Seq(a,b),_,_) if isZero(a) && isUInt(b) => zero
+        case DoPrim(Geq, Seq(a,b),_,_) if isUInt(a) && isZero(b) => one
         case e => e
       }
     }
@@ -181,15 +181,15 @@ object ConstProp extends Pass {
           def r1 = range(e.args(1))
           e.op match {
             // Always true
-            case Lt  if (r0 < r1) => one
-            case Leq if (r0 <= r1) => one
-            case Gt  if (r0 > r1) => one
-            case Geq if (r0 >= r1) => one
+            case Lt  if r0 < r1 => one
+            case Leq if r0 <= r1 => one
+            case Gt  if r0 > r1 => one
+            case Geq if r0 >= r1 => one
             // Always false
-            case Lt  if (r0 >= r1) => zero
-            case Leq if (r0 > r1) => zero
-            case Gt  if (r0 <= r1) => zero
-            case Geq if (r0 < r1) => zero
+            case Lt  if r0 >= r1 => zero
+            case Leq if r0 > r1 => zero
+            case Gt  if r0 <= r1 => zero
+            case Geq if r0 < r1 => zero
             case _ => e
           }
         case e => e
diff --git a/src/main/scala/firrtl/passes/InferTypes.scala b/src/main/scala/firrtl/passes/InferTypes.scala
index 79200a58..5daa15b1 100644
--- a/src/main/scala/firrtl/passes/InferTypes.scala
+++ b/src/main/scala/firrtl/passes/InferTypes.scala
@@ -96,7 +96,7 @@ object InferTypes extends Pass {
       m map infer_types_p(types) map infer_types_s(types)
     }
  
-    c copy (modules = (c.modules map infer_types))
+    c copy (modules = c.modules map infer_types)
   }
 }
 
@@ -110,7 +110,7 @@ object CInferTypes extends Pass {
 
     def infer_types_e(types: TypeMap)(e: Expression) : Expression =
       e map infer_types_e(types) match {
-         case (e: Reference) => e copy (tpe = (types getOrElse (e.name, UnknownType)))
+         case (e: Reference) => e copy (tpe = types.getOrElse(e.name, UnknownType))
          case (e: SubField) => e copy (tpe = field_type(e.expr.tpe, e.name))
          case (e: SubIndex) => e copy (tpe = sub_type(e.expr.tpe))
          case (e: SubAccess) => e copy (tpe = sub_type(e.expr.tpe))
@@ -156,6 +156,6 @@ object CInferTypes extends Pass {
       m map infer_types_p(types) map infer_types_s(types)
     }
    
-    c copy (modules = (c.modules map infer_types))
+    c copy (modules = c.modules map infer_types)
   }
 }
diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala
index bf1f53b4..50455283 100644
--- a/src/main/scala/firrtl/passes/InferWidths.scala
+++ b/src/main/scala/firrtl/passes/InferWidths.scala
@@ -80,7 +80,7 @@ object InferWidths extends Pass {
       //;println-all-debug(["Substituting for [" w "]"])
       val wx = simplify(w)
       //;println-all-debug(["After Simplify: [" wx "]"])
-      (wx map substitute(h)) match {
+      wx map substitute(h) match {
         //;("matched  println-debugvarwidth!")
         case w: VarWidth => h get w.name match {
           case None => w
@@ -106,7 +106,7 @@ object InferWidths extends Pass {
 
     def remove_cycle(n: String)(w: Width): Width = {
       //;println-all-debug(["Removing cycle for " n " inside " w])
-      (w map remove_cycle(n)) match {
+      w map remove_cycle(n) match {
         case w: MaxWidth => MaxWidth(w.args filter {
           case w: VarWidth => !(n equals w.name)
           case w => true
diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala
index 70631cc3..5e8ecdf9 100644
--- a/src/main/scala/firrtl/passes/LowerTypes.scala
+++ b/src/main/scala/firrtl/passes/LowerTypes.scala
@@ -218,6 +218,6 @@ object LowerTypes extends Pass {
     }
   }
 
-  def run(c: Circuit): Circuit = c copy (modules = (c.modules map lowerTypes))
+  def run(c: Circuit): Circuit = c copy (modules = c.modules map lowerTypes)
 }
 
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala
index f930307c..55e7f79b 100644
--- a/src/main/scala/firrtl/passes/PadWidths.scala
+++ b/src/main/scala/firrtl/passes/PadWidths.scala
@@ -60,5 +60,5 @@ object PadWidths extends Pass {
     case s => s map onStmt
   }
 
-  def run(c: Circuit): Circuit = c copy (modules = (c.modules map (_ map onStmt)))
+  def run(c: Circuit): Circuit = c copy (modules = c.modules map (_ map onStmt))
 }
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index dc0eb2a0..06ec8a6d 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -59,7 +59,7 @@ class Errors {
 object ToWorkingIR extends Pass {
   def name = "Working IR"
 
-  def toExp(e: Expression): Expression = e map (toExp) match {
+  def toExp(e: Expression): Expression = e map toExp match {
     case e: Reference => WRef(e.name, e.tpe, NodeKind, UNKNOWNGENDER)
     case e: SubField => WSubField(e.expr, e.name, e.tpe, UNKNOWNGENDER)
     case e: SubIndex => WSubIndex(e.expr, e.value, e.tpe, UNKNOWNGENDER)
@@ -67,20 +67,20 @@ object ToWorkingIR extends Pass {
     case e => e
   }
 
-  def toStmt(s: Statement): Statement = s map (toExp) match {
+  def toStmt(s: Statement): Statement = s map toExp match {
     case s: DefInstance => WDefInstance(s.info, s.name, s.module, UnknownType)
-    case s => s map (toStmt)
+    case s => s map toStmt
   }
 
   def run (c:Circuit): Circuit =
-    c copy (modules = (c.modules map (_ map toStmt)))
+    c copy (modules = c.modules map (_ map toStmt))
 }
 
 object PullMuxes extends Pass {
    def name = "Pull Muxes"
    def run(c: Circuit): Circuit = {
      def pull_muxes_e(e: Expression): Expression = {
-       val ex = e map (pull_muxes_e) match {
+       val ex = e map pull_muxes_e match {
          case (e: WSubField) => e.exp match {
            case (ex: Mux) => Mux(ex.cond,
               WSubField(ex.tval, e.name, e.tpe, e.gender),
@@ -107,9 +107,9 @@ object PullMuxes extends Pass {
          }
          case (e) => e
        }
-       ex map (pull_muxes_e)
+       ex map pull_muxes_e
      }
-     def pull_muxes(s: Statement): Statement = s map (pull_muxes) map (pull_muxes_e)
+     def pull_muxes(s: Statement): Statement = s map pull_muxes map pull_muxes_e
      val modulesx = c.modules.map {
        case (m:Module) => Module(m.info, m.name, m.ports, pull_muxes(m.body))
        case (m:ExtModule) => m
@@ -124,7 +124,7 @@ object ExpandConnects extends Pass {
     def expand_connects(m: Module): Module = {
       val genders = collection.mutable.LinkedHashMap[String,Gender]()
       def expand_s(s: Statement): Statement = {
-        def set_gender(e: Expression): Expression = e map (set_gender) match {
+        def set_gender(e: Expression): Expression = e map set_gender match {
           case (e: WRef) => WRef(e.name, e.tpe, e.kind, genders(e.name))
           case (e: WSubField) =>
             val f = get_field(e.exp.tpe, e.name)
@@ -172,7 +172,7 @@ object ExpandConnects extends Pass {
                  case Flip => Connect(s.info, exps(y), locs(x))
               }
             })
-          case (s) => s map (expand_s)
+          case (s) => s map expand_s
         }
       }
 
@@ -221,9 +221,9 @@ object Legalize extends Pass {
     }
   }
   private def legalizePad(expr: DoPrim): Expression = expr.args.head match {
-    case UIntLiteral(value, IntWidth(width)) if (width < expr.consts.head) =>
+    case UIntLiteral(value, IntWidth(width)) if width < expr.consts.head =>
       UIntLiteral(value, IntWidth(expr.consts.head))
-    case SIntLiteral(value, IntWidth(width)) if (width < expr.consts.head) =>
+    case SIntLiteral(value, IntWidth(width)) if width < expr.consts.head =>
       SIntLiteral(value, IntWidth(expr.consts.head))
     case _ => expr
   }
@@ -258,7 +258,7 @@ object Legalize extends Pass {
       }
       legalizedStmt map legalizeS map legalizeE
     }
-    c copy (modules = (c.modules map (_ map legalizeS)))
+    c copy (modules = c.modules map (_ map legalizeS))
   }
 }
 
@@ -286,7 +286,7 @@ object VerilogWrap extends Pass {
   }
 
   def run(c: Circuit): Circuit =
-    c copy (modules = (c.modules map (_ map vWrapS)))
+    c copy (modules = c.modules map (_ map vWrapS))
 }
 
 object VerilogRename extends Pass {
@@ -306,7 +306,7 @@ object VerilogRename extends Pass {
     p copy (name = verilogRenameN(p.name))
 
   def run(c: Circuit): Circuit =
-    c copy (modules = (c.modules map (_ map verilogRenameP map verilogRenameS)))
+    c copy (modules = c.modules map (_ map verilogRenameP map verilogRenameS))
 }
 
 
diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala
index 16a4d928..c309d870 100644
--- a/src/main/scala/firrtl/passes/RemoveAccesses.scala
+++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala
@@ -90,7 +90,7 @@ object RemoveAccesses extends Pass {
           */
         val stmts = mutable.ArrayBuffer[Statement]()
         def removeMale(e: Expression): Expression = e match {
-          case (_:WSubAccess| _: WSubField| _: WSubIndex| _: WRef) if (hasAccess(e)) => 
+          case (_:WSubAccess| _: WSubField| _: WSubIndex| _: WRef) if hasAccess(e) =>
             val rs = getLocations(e)
             rs find (x => x.guard != one) match {
               case None => error("Shouldn't be here")
@@ -113,7 +113,7 @@ object RemoveAccesses extends Pass {
         /** Replaces a subaccess in a given female expression
           */
         def removeFemale(info: Info, loc: Expression): Expression = loc match {
-          case (_: WSubAccess| _: WSubField| _: WSubIndex| _: WRef) if (hasAccess(loc)) => 
+          case (_: WSubAccess| _: WSubField| _: WSubIndex| _: WRef) if hasAccess(loc) =>
             val ls = getLocations(loc)
             if (ls.size == 1 & weq(ls.head.guard,one)) loc
             else {
@@ -149,7 +149,7 @@ object RemoveAccesses extends Pass {
         val sx = s match {
           case Connect(info, loc, exp) =>
             Connect(info, removeFemale(info, fixFemale(loc)), fixMale(exp))
-          case (s) => s map (fixMale) map (onStmt)
+          case (s) => s map fixMale map onStmt
         }
         stmts += sx
         if (stmts.size != 1) Block(stmts) else stmts(0)
@@ -157,9 +157,9 @@ object RemoveAccesses extends Pass {
       Module(m.info, m.name, m.ports, squashEmpty(onStmt(m.body)))
     }
   
-    c copy (modules = (c.modules map {
+    c copy (modules = c.modules map {
       case m: ExtModule => m
       case m: Module => remove_m(m)
-    }))
+    })
   }
 }
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
index 8c158da9..9d218dd6 100644
--- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
+++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
@@ -56,7 +56,7 @@ object RemoveCHIRRTL extends Pass {
       (e1s zip e2s) map { case (e1, e2) => Mux(e.cond, e1, e2, mux_type(e1, e2)) }
     case (e: ValidIf) =>
       create_exps(e.value) map (e1 => ValidIf(e.cond, e1, e1.tpe))
-    case (e) => (e.tpe) match {
+    case (e) => e.tpe match {
       case (_: GroundType) => Seq(e)
       case (t: BundleType) => (t.fields foldLeft Seq[Expression]())((exps, f) =>
         exps ++ create_exps(SubField(e, f.name, f.tpe)))
@@ -187,7 +187,7 @@ object RemoveCHIRRTL extends Pass {
         remove_chirrtl_e(g)(expr), remove_chirrtl_e(MALE)(index), tpe)
       case e => e map remove_chirrtl_e(g)
    }
-   (s) match {
+   s match {
       case DefNode(info, name, value) =>
         val valuex = remove_chirrtl_e(MALE)(value)
         val sx = DefNode(info, name, valuex)
@@ -250,5 +250,5 @@ object RemoveCHIRRTL extends Pass {
   }
 
   def run(c: Circuit): Circuit =
-    c copy (modules = (c.modules map remove_chirrtl_m))
+    c copy (modules = c.modules map remove_chirrtl_m)
 }
diff --git a/src/main/scala/firrtl/passes/ReplSeqMem.scala b/src/main/scala/firrtl/passes/ReplSeqMem.scala
index 3b51d73f..62546a84 100644
--- a/src/main/scala/firrtl/passes/ReplSeqMem.scala
+++ b/src/main/scala/firrtl/passes/ReplSeqMem.scala
@@ -88,7 +88,7 @@ Optional Arguments:
     error("No circuit name specified for ReplSeqMem!" + usage)
   )
   val target = CircuitName(passCircuit)
-  def duplicate(n: Named) = this copy (t = (t replace (s"-c:$passCircuit", s"-c:${n.name}")))
+  def duplicate(n: Named) = this copy (t = t.replace(s"-c:$passCircuit", s"-c:${n.name}"))
 }
 
 class ReplSeqMem(transID: TransID) extends Transform with SimpleRun {
diff --git a/src/main/scala/firrtl/passes/Resolves.scala b/src/main/scala/firrtl/passes/Resolves.scala
index 49df9ba6..1fad9b05 100644
--- a/src/main/scala/firrtl/passes/Resolves.scala
+++ b/src/main/scala/firrtl/passes/Resolves.scala
@@ -67,7 +67,7 @@ object ResolveKinds extends Pass {
   }
  
   def run(c: Circuit): Circuit =
-    c copy (modules = (c.modules map resolve_kinds))
+    c copy (modules = c.modules map resolve_kinds)
 }
 
 object ResolveGenders extends Pass {
@@ -100,7 +100,7 @@ object ResolveGenders extends Pass {
   def resolve_gender(m: DefModule): DefModule = m map resolve_s
 
   def run(c: Circuit): Circuit =
-    c copy (modules = (c.modules map resolve_gender))
+    c copy (modules = c.modules map resolve_gender)
 }
 
 object CInferMDir extends Pass {
@@ -108,7 +108,7 @@ object CInferMDir extends Pass {
   type MPortDirMap = collection.mutable.LinkedHashMap[String, MPortDir]
 
   def infer_mdir_e(mports: MPortDirMap, dir: MPortDir)(e: Expression): Expression = {
-    (e map infer_mdir_e(mports, dir)) match {
+    e map infer_mdir_e(mports, dir) match {
       case e: Reference => mports get e.name match {
         case Some(p) => mports(e.name) = (p, dir) match {
           case (MInfer, MInfer) => Utils.error("Shouldn't be here")
@@ -160,5 +160,5 @@ object CInferMDir extends Pass {
   }
      
   def run(c: Circuit): Circuit =
-    c copy (modules = (c.modules map infer_mdir))
+    c copy (modules = c.modules map infer_mdir)
 }
diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala
index a5eee002..ebd3c871 100644
--- a/src/main/scala/firrtl/passes/Uniquify.scala
+++ b/src/main/scala/firrtl/passes/Uniquify.scala
@@ -234,17 +234,17 @@ object Uniquify extends Pass {
           val newFields = tpe.fields map ( f =>
             DefMemory(s.info, f.name, f.tpe, s.depth, s.writeLatency,
               s.readLatency, s.readers, s.writers, s.readwriters)
-          ) flatMap (recStmtToType)
+          ) flatMap recStmtToType
           Seq(Field(s.name, Default, BundleType(newFields)))
         case tpe: VectorType =>
           val newFields = (0 until tpe.size) map ( i =>
             s.copy(name = i.toString, dataType = tpe.tpe)
-          ) flatMap (recStmtToType)
+          ) flatMap recStmtToType
           Seq(Field(s.name, Default, BundleType(newFields)))
       }
       case s: DefNode => Seq(Field(s.name, Default, s.value.tpe))
       case s: Conditionally => recStmtToType(s.conseq) ++ recStmtToType(s.alt)
-      case s: Block => (s.stmts map (recStmtToType)).flatten
+      case s: Block => (s.stmts map recStmtToType).flatten
       case s => Seq()
     }
     BundleType(recStmtToType(s))
@@ -266,10 +266,10 @@ object Uniquify extends Pass {
       def uniquifyExp(e: Expression): Expression = e match {
         case (_: WRef | _: WSubField | _: WSubIndex | _: WSubAccess ) =>
           uniquifyNamesExp(e, nameMap.toMap)
-        case e: Mux => e map (uniquifyExp)
-        case e: ValidIf => e map (uniquifyExp)
+        case e: Mux => e map uniquifyExp
+        case e: ValidIf => e map uniquifyExp
         case (_: UIntLiteral | _: SIntLiteral) => e
-        case e: DoPrim => e map (uniquifyExp)
+        case e: DoPrim => e map uniquifyExp
       }
 
       def uniquifyStmt(s: Statement): Statement = {
@@ -342,7 +342,7 @@ object Uniquify extends Pass {
           // Adds port names to namespace and namemap
           nameMap ++= portNameMap(m.name)
           namespace ++= create_exps("", portTypeMap(m.name)) map
-                        (LowerTypes.loweredName) map (_.tail)
+                        LowerTypes.loweredName map (_.tail)
           m.copy(body = uniquifyBody(m.body) )
       }
     }
diff --git a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala
index 675494b4..c3660fe0 100644
--- a/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala
+++ b/src/main/scala/firrtl/passes/UpdateDuplicateMemMacros.scala
@@ -150,6 +150,6 @@ object UpdateDuplicateMemMacros extends Pass {
        map updateStmtRefs(memPortMap))
   }
 
-  def run(c: Circuit) = c copy (modules = (c.modules map updateMemMods)) 
+  def run(c: Circuit) = c copy (modules = c.modules map updateMemMods)
 }
 // TODO: Module namespace?
diff --git a/src/main/scala/firrtl/passes/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/VerilogMemDelays.scala
index 325e4ba2..908f757e 100644
--- a/src/main/scala/firrtl/passes/VerilogMemDelays.scala
+++ b/src/main/scala/firrtl/passes/VerilogMemDelays.scala
@@ -72,8 +72,8 @@ object VerilogMemDelays extends Pass {
       // 2. memories are transformed into combinational
       //    because latency pipes are added for longer latencies
       val mem = s copy (
-        readers = (s.readers ++ (s.readwriters map (rw => rwMap(rw)._1))),
-        writers = (s.writers ++ (s.readwriters map (rw => rwMap(rw)._2))),
+        readers = s.readers ++ (s.readwriters map (rw => rwMap(rw)._1)),
+        writers = s.writers ++ (s.readwriters map (rw => rwMap(rw)._2)),
         readwriters = Nil, readLatency = 0, writeLatency = 1)
       def pipe(e: Expression, // Expression to be piped
                n: Int, // pipe depth
@@ -180,5 +180,5 @@ object VerilogMemDelays extends Pass {
   }
 
   def run(c: Circuit): Circuit =
-    c copy (modules = (c.modules map memDelayMod))
+    c copy (modules = c.modules map memDelayMod)
 }