[2.13] convert toSeq and toMap where necessary to compile

11 files changed, 23 insertions, 21 deletions

diff --git a/src/main/scala/firrtl/passes/CheckHighForm.scala b/src/main/scala/firrtl/passes/CheckHighForm.scala
index 512602cf..fb5dd1ca 100644
--- a/src/main/scala/firrtl/passes/CheckHighForm.scala
+++ b/src/main/scala/firrtl/passes/CheckHighForm.scala
@@ -96,7 +96,7 @@ trait CheckHighFormLike { this: Pass =>
 
     val intModuleNames = c.modules.view.collect({ case m: Module => m.name }).toSet
 
-    c.modules.view.groupBy(_.name).filter(_._2.length > 1).flatMap(_._2).foreach {
+    c.modules.groupBy(_.name).filter(_._2.length > 1).flatMap(_._2).foreach {
       m => errors.append(new ModuleNameNotUniqueException(m.info, m.name))
     }
 
diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala
index 1eb16a9b..4a5577f9 100644
--- a/src/main/scala/firrtl/passes/CheckInitialization.scala
+++ b/src/main/scala/firrtl/passes/CheckInitialization.scala
@@ -57,7 +57,7 @@ object CheckInitialization extends Pass {
           case _ => e.foreach(hasVoid)
         }
         hasVoid(e)
-        (void, voidDeps)
+        (void, voidDeps.toSeq)
       }
       def checkInitS(s: Statement): Unit = {
         s match {
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index ab4c9bfa..3c1ff675 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -210,7 +210,7 @@ object ExpandWhens extends Pass {
 
     val attachedAnalogs = attaches.flatMap(_.exprs.map(we)).toSet
     val newBody = Block(Seq(squashEmpty(bodyx)) ++ expandNetlist(netlist, attachedAnalogs) ++
-                            combineAttaches(attaches) ++ simlist)
+                            combineAttaches(attaches.toSeq) ++ simlist)
     Module(m.info, m.name, m.ports, newBody)
   }
 
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index ec674c19..39cb4b9c 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -106,11 +106,11 @@ class InlineInstances extends Transform with DependencyAPIMigration with Registe
       }
 
       moduleNames.foreach{mn => checkExists(mn.name)}
-      if (errors.nonEmpty) throw new PassExceptions(errors)
+      if (errors.nonEmpty) throw new PassExceptions(errors.toSeq)
       moduleNames.foreach{mn => checkExternal(mn.name)}
-      if (errors.nonEmpty) throw new PassExceptions(errors)
+      if (errors.nonEmpty) throw new PassExceptions(errors.toSeq)
       instanceNames.foreach{cn => checkInstance(cn)}
-      if (errors.nonEmpty) throw new PassExceptions(errors)
+      if (errors.nonEmpty) throw new PassExceptions(errors.toSeq)
    }
 
 
diff --git a/src/main/scala/firrtl/passes/Pass.scala b/src/main/scala/firrtl/passes/Pass.scala
index 4b7a34bf..036bd06a 100644
--- a/src/main/scala/firrtl/passes/Pass.scala
+++ b/src/main/scala/firrtl/passes/Pass.scala
@@ -23,6 +23,6 @@ class Errors {
     case 1 => throw errors.head
     case _ =>
       append(new PassException(s"${errors.length} errors detected!"))
-      throw new PassExceptions(errors)
+      throw new PassExceptions(errors.toSeq)
   }
 }
diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala
index f571bf28..18db5939 100644
--- a/src/main/scala/firrtl/passes/RemoveAccesses.scala
+++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala
@@ -168,7 +168,7 @@ object RemoveAccesses extends Pass {
           case sxx => sxx map fixSource map onStmt
         }
         stmts += sx
-        if (stmts.size != 1) Block(stmts) else stmts(0)
+        if (stmts.size != 1) Block(stmts.toSeq) else stmts(0)
       }
       Module(m.info, m.name, m.ports, squashEmpty(onStmt(m.body)))
     }
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
index 87a43ce3..cd801570 100644
--- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
+++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
@@ -10,6 +10,8 @@ import firrtl.Utils._
 import firrtl.Mappers._
 import firrtl.options.Dependency
 
+import scala.collection.mutable
+
 case class MPort(name: String, clk: Expression)
 case class MPorts(readers: ArrayBuffer[MPort], writers: ArrayBuffer[MPort], readwriters: ArrayBuffer[MPort])
 case class DataRef(exp: Expression, source: String, sink: String, mask: String, rdwrite: Boolean)
@@ -80,14 +82,14 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration {
       types(sx.name) = sx.tpe
       val taddr = UIntType(IntWidth(1 max getUIntWidth(sx.size - 1)))
       val tdata = sx.tpe
-      def set_poison(vec: Seq[MPort]) = vec flatMap (r => Seq(
+      def set_poison(vec: mutable.Seq[MPort]) = vec.toSeq.flatMap (r => Seq(
         IsInvalid(sx.info, SubField(SubField(Reference(sx.name, ut), r.name, ut), "addr", taddr)),
         IsInvalid(sx.info, SubField(SubField(Reference(sx.name, ut), r.name, ut), "clk", ClockType))
       ))
-      def set_enable(vec: Seq[MPort], en: String) = vec map (r =>
+      def set_enable(vec: mutable.Seq[MPort], en: String) = vec.toSeq.map (r =>
         Connect(sx.info, SubField(SubField(Reference(sx.name, ut), r.name, ut), en, BoolType), zero)
       )
-      def set_write(vec: Seq[MPort], data: String, mask: String) = vec flatMap { r =>
+      def set_write(vec: mutable.Seq[MPort], data: String, mask: String) = vec.toSeq.flatMap { r =>
         val tmask = createMask(sx.tpe)
         val portRef = SubField(Reference(sx.name, ut), r.name, ut)
         Seq(IsInvalid(sx.info, SubField(portRef, data, tdata)), IsInvalid(sx.info, SubField(portRef, mask, tmask)))
@@ -105,7 +107,7 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration {
         set_enable(rws, "en") ++
         set_write(rws, "wdata", "wmask")
       val mem = DefMemory(sx.info, sx.name, sx.tpe, sx.size, 1, if (sx.seq) 1 else 0,
-                  rds map (_.name), wrs map (_.name), rws map (_.name), sx.readUnderWrite)
+                  rds.map(_.name).toSeq, wrs.map(_.name).toSeq, rws.map(_.name).toSeq, sx.readUnderWrite)
       Block(mem +: stmts)
     case sx: CDefMPort =>
       types.get(sx.mem) match {
@@ -162,8 +164,8 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration {
           }
         case MInfer => // do nothing if it's not being used
       }
-      Block(
-        (addrs map (x => Connect(sx.info, SubField(portRef, x, ut), sx.exps.head))) ++
+      Block(List() ++
+        (addrs.map (x => Connect(sx.info, SubField(portRef, x, ut), sx.exps.head))) ++
         (clks map (x => Connect(sx.info, SubField(portRef, x, ut), sx.exps(1)))) ++
         (ens map (x => Connect(sx.info,SubField(portRef, x, ut), one))) ++
          masks.map(lhs => Connect(sx.info, lhs, zero))
@@ -233,7 +235,7 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration {
             case Some(wmode) => stmts += Connect(info, wmode, one)
           }
         }
-        if (stmts.isEmpty) sx else Block(sx +: stmts)
+        if (stmts.isEmpty) sx else Block(sx +: stmts.toSeq)
       case PartialConnect(info, loc, expr) =>
         val locx = remove_chirrtl_e(SinkFlow)(loc)
         val rocx = remove_chirrtl_e(SourceFlow)(expr)
@@ -252,7 +254,7 @@ object RemoveCHIRRTL extends Transform with DependencyAPIMigration {
             case Some(wmode) => stmts += Connect(info, wmode, one)
           }
         }
-        if (stmts.isEmpty) sx else Block(sx +: stmts)
+        if (stmts.isEmpty) sx else Block(sx +: stmts.toSeq)
       case sx => sx map remove_chirrtl_s(refs, raddrs) map remove_chirrtl_e(SourceFlow)
     }
   }
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
index 03c295ed..4847a698 100644
--- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
@@ -135,7 +135,7 @@ object InferReadWritePass extends Pass {
     (m map inferReadWriteStmt(connects, repl, stmts)
        map replaceStmt(repl)) match {
       case m: ExtModule => m
-      case m: Module => m copy (body = Block(m.body +: stmts))
+      case m: Module => m copy (body = Block(m.body +: stmts.toSeq))
     }
   }
 
diff --git a/src/main/scala/firrtl/passes/memlib/MemConf.scala b/src/main/scala/firrtl/passes/memlib/MemConf.scala
index 4d6ba2c6..5db7de61 100644
--- a/src/main/scala/firrtl/passes/memlib/MemConf.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemConf.scala
@@ -22,7 +22,7 @@ object MemPort {
     s.split(",").toSeq.map(MemPort.apply).map(_ match {
       case Some(x) => x
       case _ => throw new Exception(s"Error parsing MemPort string : ${s}")
-    }).groupBy(identity).mapValues(_.size)
+    }).groupBy(identity).mapValues(_.size).toMap
   }
 }
 
@@ -64,6 +64,6 @@ object MemConf {
       (if (writePorts == 0) Map.empty[MemPort, Int] else Map(MaskedWritePort -> writePorts)) ++
       (if (readWritePorts == 0) Map.empty[MemPort, Int] else Map(MaskedReadWritePort -> readWritePorts))
     }) ++ (if (readPorts == 0) Map.empty[MemPort, Int] else Map(ReadPort -> readPorts))
-    return new MemConf(name, depth, width, ports, maskGranularity)
+    new MemConf(name, depth, width, ports, maskGranularity)
   }
 }
diff --git a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala
index 29200631..b5ff10c6 100644
--- a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala
+++ b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala
@@ -72,7 +72,7 @@ class ResolveMemoryReference extends Transform with DependencyAPIMigration {
     val noDedups = state.annotations.collect {
       case NoDedupMemAnnotation(ComponentName(cn, ModuleName(mn, _))) => mn -> cn
     }
-    val noDedupMap: Map[String, Set[String]] = noDedups.groupBy(_._1).mapValues(_.map(_._2).toSet)
+    val noDedupMap: Map[String, Set[String]] = noDedups.groupBy(_._1).mapValues(_.map(_._2).toSet).toMap
     state.copy(circuit = run(state.circuit, noDedupMap))
   }
 }
diff --git a/src/main/scala/firrtl/passes/wiring/Wiring.scala b/src/main/scala/firrtl/passes/wiring/Wiring.scala
index 1ee509e2..c62a565e 100644
--- a/src/main/scala/firrtl/passes/wiring/Wiring.scala
+++ b/src/main/scala/firrtl/passes/wiring/Wiring.scala
@@ -196,7 +196,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
               case Block(sx) => sx
               case s => Seq(s)
             }
-            Module(i, n, ps ++ ports, Block(defines ++ stmts ++ connects))
+            Module(i, n, ps ++ ports, Block(List() ++ defines ++ stmts ++ connects))
           case ExtModule(i, n, ps, dn, p) => ExtModule(i, n, ps ++ ports, dn, p)
         }
     }