diff options
| author | Adam Izraelevitz | 2017-03-23 16:16:24 -0700 |
|---|---|---|
| committer | GitHub | 2017-03-23 16:16:24 -0700 |
| commit | 67eb4e2de6166b8f1eb5190215640117b82e8c48 (patch) | |
| tree | 18cbaf901eff58262d833bf5bc0d75262c9ab57d /src/main/scala/firrtl/passes/wiring | |
| parent | 4cffd184397905eeb79e2df0913b4ded97dc8558 (diff) | |
Pass now subclasses Transform (#477)
Diffstat (limited to 'src/main/scala/firrtl/passes/wiring')
| -rw-r--r-- | src/main/scala/firrtl/passes/wiring/Wiring.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/wiring/WiringTransform.scala | 6 |
2 files changed, 3 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/passes/wiring/Wiring.scala b/src/main/scala/firrtl/passes/wiring/Wiring.scala index f5da4c06..9656abb2 100644 --- a/src/main/scala/firrtl/passes/wiring/Wiring.scala +++ b/src/main/scala/firrtl/passes/wiring/Wiring.scala @@ -17,7 +17,6 @@ case class WiringException(msg: String) extends PassException(msg) case class WiringInfo(source: String, comp: String, sinks: Set[String], pin: String, top: String) class Wiring(wiSeq: Seq[WiringInfo]) extends Pass { - def name = this.getClass.getSimpleName def run(c: Circuit): Circuit = { wiSeq.foldLeft(c) { (circuit, wi) => wire(circuit, wi) } } diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala index 2c122943..a8ef5f58 100644 --- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala +++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala @@ -60,10 +60,10 @@ object TopAnnotation { * Notes: * - No module uniquification occurs (due to imposed restrictions) */ -class WiringTransform extends Transform with SimpleRun { +class WiringTransform extends Transform { def inputForm = MidForm def outputForm = MidForm - def passSeq(wis: Seq[WiringInfo]) = + def transforms(wis: Seq[WiringInfo]) = Seq(new Wiring(wis), InferTypes, ResolveKinds, @@ -89,7 +89,7 @@ class WiringTransform extends Transform with SimpleRun { val wis = tops.foldLeft(Seq[WiringInfo]()) { case (seq, (pin, top)) => seq :+ WiringInfo(sources(pin), comp(pin), sinks(pin), pin, top) } - state.copy(circuit = runPasses(state.circuit, passSeq(wis))) + transforms(wis).foldLeft(state) { (in, xform) => xform.runTransform(in) } case _ => error("Wrong number of sources, tops, or sinks!") } } |
