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authorJack Koenig2021-01-19 20:19:08 -0800
committerGitHub2021-01-20 04:19:08 +0000
commit031fe1382660867750e6eeebea5665c137dbccbe (patch)
treecc65ca17a57fe093a73a5c25059f42cd22332a76 /src/main/scala/firrtl/passes/wiring
parent698a9dca52f819aca6309e3b03f2420a71bc89a6 (diff)
Cleanup some warnings (#2032)
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/wiring')
-rw-r--r--src/main/scala/firrtl/passes/wiring/WiringUtils.scala2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
index d926f6a9..cab6aa5f 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
@@ -90,8 +90,6 @@ object WiringUtils {
def getChildrenMap(c: Circuit): ChildrenMap = {
val childrenMap = new ChildrenMap()
def getChildren(mname: String)(s: Statement): Unit = s match {
- case s: WDefInstance =>
- childrenMap(mname) = childrenMap(mname) :+ ((s.name, s.module))
case s: DefInstance =>
childrenMap(mname) = childrenMap(mname) :+ ((s.name, s.module))
case s => s.foreach(getChildren(mname))