All of src/ formatted with scalafmt

3 files changed, 181 insertions, 164 deletions

diff --git a/src/main/scala/firrtl/passes/wiring/Wiring.scala b/src/main/scala/firrtl/passes/wiring/Wiring.scala
index 3f74e5d2..a69b7797 100644
--- a/src/main/scala/firrtl/passes/wiring/Wiring.scala
+++ b/src/main/scala/firrtl/passes/wiring/Wiring.scala
@@ -18,8 +18,7 @@ import firrtl.graph.EulerTour
 case class WiringInfo(source: ComponentName, sinks: Seq[Named], pin: String)
 
 /** A data store of wiring names */
-case class WiringNames(compName: String, source: String, sinks: Seq[Named],
-                       pin: String)
+case class WiringNames(compName: String, source: String, sinks: Seq[Named], pin: String)
 
 /** Pass that computes and applies a sequence of wiring modifications
   *
@@ -28,31 +27,39 @@ case class WiringNames(compName: String, source: String, sinks: Seq[Named],
   */
 class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
   def run(c: Circuit): Circuit = analyze(c)
-    .foldLeft(c){
-      case (cx, (tpe, modsMap)) => cx.copy(
-        modules = cx.modules map onModule(tpe, modsMap)) }
+    .foldLeft(c) {
+      case (cx, (tpe, modsMap)) => cx.copy(modules = cx.modules.map(onModule(tpe, modsMap)))
+    }
 
   /** Converts multiple units of wiring information to module modifications */
   private def analyze(c: Circuit): Seq[(Type, Map[String, Modifications])] = {
 
     val names = wiSeq
-      .map ( wi => (wi.source, wi.sinks, wi.pin) match {
-              case (ComponentName(comp, ModuleName(source,_)), sinks, pin) =>
-                WiringNames(comp, source, sinks, pin) })
+      .map(wi =>
+        (wi.source, wi.sinks, wi.pin) match {
+          case (ComponentName(comp, ModuleName(source, _)), sinks, pin) =>
+            WiringNames(comp, source, sinks, pin)
+        }
+      )
 
     val portNames = mutable.Seq.fill(names.size)(Map[String, String]())
-    c.modules.foreach{ m =>
+    c.modules.foreach { m =>
       val ns = Namespace(m)
-      names.zipWithIndex.foreach{ case (WiringNames(c, so, si, p), i) =>
-        portNames(i) = portNames(i) +
-        ( m.name -> {
-           if (si.exists(getModuleName(_) == m.name)) ns.newName(p)
-           else ns.newName(tokenize(c) filterNot ("[]." contains _) mkString "_")
-         })}}
+      names.zipWithIndex.foreach {
+        case (WiringNames(c, so, si, p), i) =>
+          portNames(i) = portNames(i) +
+            (m.name -> {
+              if (si.exists(getModuleName(_) == m.name)) ns.newName(p)
+              else ns.newName(tokenize(c).filterNot("[]." contains _).mkString("_"))
+            })
+      }
+    }
 
     val iGraph = InstanceKeyGraph(c)
-    names.zip(portNames).map{ case(WiringNames(comp, so, si, _), pn) =>
-      computeModifications(c, iGraph, comp, so, si, pn) }
+    names.zip(portNames).map {
+      case (WiringNames(comp, so, si, _), pn) =>
+        computeModifications(c, iGraph, comp, so, si, pn)
+    }
   }
 
   /** Converts a single unit of wiring information to module modifications
@@ -69,19 +76,20 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
     * @return a tuple of the component type and a map of module names
     * to pending modifications
     */
-  private def computeModifications(c: Circuit,
-                                   iGraph: InstanceKeyGraph,
-                                   compName: String,
-                                   source: String,
-                                   sinks: Seq[Named],
-                                   portNames: Map[String, String]):
-      (Type, Map[String, Modifications]) = {
+  private def computeModifications(
+    c:         Circuit,
+    iGraph:    InstanceKeyGraph,
+    compName:  String,
+    source:    String,
+    sinks:     Seq[Named],
+    portNames: Map[String, String]
+  ): (Type, Map[String, Modifications]) = {
 
     val sourceComponentType = getType(c, source, compName)
-    val sinkComponents: Map[String, Seq[String]] = sinks
-      .collect{ case ComponentName(c, ModuleName(m, _)) => (c, m) }
-      .foldLeft(new scala.collection.immutable.HashMap[String, Seq[String]]){
-        case (a, (c, m)) => a ++ Map(m -> (Seq(c) ++ a.getOrElse(m, Nil)) ) }
+    val sinkComponents: Map[String, Seq[String]] = sinks.collect { case ComponentName(c, ModuleName(m, _)) => (c, m) }
+      .foldLeft(new scala.collection.immutable.HashMap[String, Seq[String]]) {
+        case (a, (c, m)) => a ++ Map(m -> (Seq(c) ++ a.getOrElse(m, Nil)))
+      }
 
     // Determine "ownership" of sources to sinks via minimum distance
     val owners = sinksToSourcesSeq(sinks, source, iGraph)
@@ -95,86 +103,88 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
     def makeWire(m: Modifications, portName: String): Modifications =
       m.copy(addPortOrWire = Some(m.addPortOrWire.getOrElse((portName, DecWire))))
     def makeWireC(m: Modifications, portName: String, c: (String, String)): Modifications =
-      m.copy(addPortOrWire = Some(m.addPortOrWire.getOrElse((portName, DecWire))), cons = (m.cons :+ c).distinct )
+      m.copy(addPortOrWire = Some(m.addPortOrWire.getOrElse((portName, DecWire))), cons = (m.cons :+ c).distinct)
 
     val tour = EulerTour(iGraph.graph, iGraph.top)
     // Finds the lowest common ancestor instances for two module names in a design
     def lowestCommonAncestor(moduleA: Seq[InstanceKey], moduleB: Seq[InstanceKey]): Seq[InstanceKey] =
       tour.rmq(moduleA, moduleB)
 
-    owners.foreach { case (sink, source) =>
-      val lca = lowestCommonAncestor(sink, source)
-
-      // Compute metadata along Sink to LCA paths.
-      sink.drop(lca.size - 1).sliding(2).toList.reverse.foreach {
-        case Seq(InstanceKey(_,pm), InstanceKey(ci,cm)) =>
-          val to = s"$ci.${portNames(cm)}"
-          val from = s"${portNames(pm)}"
-          meta(pm) = makeWireC(meta(pm), portNames(pm), (to, from))
-          meta(cm) = meta(cm).copy(
-            addPortOrWire = Some((portNames(cm), DecInput))
-          )
-        // Case where the sink is the LCA
-        case Seq(InstanceKey(_,pm)) =>
-          // Case where the source is also the LCA
-          if (source.drop(lca.size).isEmpty) {
-            meta(pm) = makeWire(meta(pm), portNames(pm))
-          } else {
-            val InstanceKey(ci,cm) = source.drop(lca.size).head
-            val to = s"${portNames(pm)}"
-            val from = s"$ci.${portNames(cm)}"
-            meta(pm) = makeWireC(meta(pm), portNames(pm), (to, from))
-          }
-      }
+    owners.foreach {
+      case (sink, source) =>
+        val lca = lowestCommonAncestor(sink, source)
 
-      // Compute metadata for the Sink
-      sink.last match { case InstanceKey( _, m) =>
-        if (sinkComponents.contains(m)) {
-          val from = s"${portNames(m)}"
-          sinkComponents(m).foreach( to =>
-            meta(m) = meta(m).copy(
-              cons = (meta(m).cons :+( (to, from) )).distinct
+        // Compute metadata along Sink to LCA paths.
+        sink.drop(lca.size - 1).sliding(2).toList.reverse.foreach {
+          case Seq(InstanceKey(_, pm), InstanceKey(ci, cm)) =>
+            val to = s"$ci.${portNames(cm)}"
+            val from = s"${portNames(pm)}"
+            meta(pm) = makeWireC(meta(pm), portNames(pm), (to, from))
+            meta(cm) = meta(cm).copy(
+              addPortOrWire = Some((portNames(cm), DecInput))
             )
-          )
+          // Case where the sink is the LCA
+          case Seq(InstanceKey(_, pm)) =>
+            // Case where the source is also the LCA
+            if (source.drop(lca.size).isEmpty) {
+              meta(pm) = makeWire(meta(pm), portNames(pm))
+            } else {
+              val InstanceKey(ci, cm) = source.drop(lca.size).head
+              val to = s"${portNames(pm)}"
+              val from = s"$ci.${portNames(cm)}"
+              meta(pm) = makeWireC(meta(pm), portNames(pm), (to, from))
+            }
         }
-      }
 
-      // Compute metadata for the Source
-      source.last match { case InstanceKey( _, m) =>
-        val to = s"${portNames(m)}"
-        val from = compName
-        meta(m) = meta(m).copy(
-          cons = (meta(m).cons :+( (to, from) )).distinct
-        )
-      }
+        // Compute metadata for the Sink
+        sink.last match {
+          case InstanceKey(_, m) =>
+            if (sinkComponents.contains(m)) {
+              val from = s"${portNames(m)}"
+              sinkComponents(m).foreach(to =>
+                meta(m) = meta(m).copy(
+                  cons = (meta(m).cons :+ ((to, from))).distinct
+                )
+              )
+            }
+        }
 
-      // Compute metadata along Source to LCA path
-      source.drop(lca.size - 1).sliding(2).toList.reverse.map {
-        case Seq(InstanceKey(_,pm), InstanceKey(ci,cm)) => {
-          val to = s"${portNames(pm)}"
-          val from = s"$ci.${portNames(cm)}"
-          meta(pm) = meta(pm).copy(
-            cons = (meta(pm).cons :+( (to, from) )).distinct
-          )
-          meta(cm) = meta(cm).copy(
-            addPortOrWire = Some((portNames(cm), DecOutput))
-          )
+        // Compute metadata for the Source
+        source.last match {
+          case InstanceKey(_, m) =>
+            val to = s"${portNames(m)}"
+            val from = compName
+            meta(m) = meta(m).copy(
+              cons = (meta(m).cons :+ ((to, from))).distinct
+            )
         }
-        // Case where the source is the LCA
-        case Seq(InstanceKey(_,pm)) => {
-          // Case where the sink is also the LCA. We do nothing here,
-          // as we've created the connecting wire above
-          if (sink.drop(lca.size).isEmpty) {
-          } else {
-            val InstanceKey(ci,cm) = sink.drop(lca.size).head
-            val to = s"$ci.${portNames(cm)}"
-            val from = s"${portNames(pm)}"
+
+        // Compute metadata along Source to LCA path
+        source.drop(lca.size - 1).sliding(2).toList.reverse.map {
+          case Seq(InstanceKey(_, pm), InstanceKey(ci, cm)) => {
+            val to = s"${portNames(pm)}"
+            val from = s"$ci.${portNames(cm)}"
             meta(pm) = meta(pm).copy(
-              cons = (meta(pm).cons :+( (to, from) )).distinct
+              cons = (meta(pm).cons :+ ((to, from))).distinct
             )
+            meta(cm) = meta(cm).copy(
+              addPortOrWire = Some((portNames(cm), DecOutput))
+            )
+          }
+          // Case where the source is the LCA
+          case Seq(InstanceKey(_, pm)) => {
+            // Case where the sink is also the LCA. We do nothing here,
+            // as we've created the connecting wire above
+            if (sink.drop(lca.size).isEmpty) {} else {
+              val InstanceKey(ci, cm) = sink.drop(lca.size).head
+              val to = s"$ci.${portNames(cm)}"
+              val from = s"${portNames(pm)}"
+              meta(pm) = meta(pm).copy(
+                cons = (meta(pm).cons :+ ((to, from))).distinct
+              )
+            }
           }
         }
-      }
     }
     (sourceComponentType, meta.toMap)
   }
@@ -189,20 +199,22 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
         val ports = mutable.ArrayBuffer[Port]()
         l.addPortOrWire match {
           case None =>
-          case Some((s, dt)) => dt match {
-            case DecInput  => ports += Port(NoInfo, s, Input, t)
-            case DecOutput => ports += Port(NoInfo, s, Output, t)
-            case DecWire   => defines += DefWire(NoInfo, s, t)
-          }
+          case Some((s, dt)) =>
+            dt match {
+              case DecInput  => ports += Port(NoInfo, s, Input, t)
+              case DecOutput => ports += Port(NoInfo, s, Output, t)
+              case DecWire   => defines += DefWire(NoInfo, s, t)
+            }
         }
-        connects ++= (l.cons map { case ((l, r)) =>
-          Connect(NoInfo, toExp(l), toExp(r))
+        connects ++= (l.cons.map {
+          case ((l, r)) =>
+            Connect(NoInfo, toExp(l), toExp(r))
         })
         m match {
           case Module(i, n, ps, body) =>
             val stmts = body match {
               case Block(sx) => sx
-              case s => Seq(s)
+              case s         => Seq(s)
             }
             Module(i, n, ps ++ ports, Block(List() ++ defines ++ stmts ++ connects))
           case ExtModule(i, n, ps, dn, p) => ExtModule(i, n, ps ++ ports, dn, p)
diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
index 20fb1215..d6658f16 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
@@ -14,14 +14,12 @@ import firrtl.stage.Forms
 case class WiringException(msg: String) extends PassException(msg)
 
 /** A component, e.g. register etc. Must be declared only once under the TopAnnotation */
-case class SourceAnnotation(target: ComponentName, pin: String) extends
-    SingleTargetAnnotation[ComponentName] {
+case class SourceAnnotation(target: ComponentName, pin: String) extends SingleTargetAnnotation[ComponentName] {
   def duplicate(n: ComponentName) = this.copy(target = n)
 }
 
 /** A module, e.g. ExtModule etc., that should add the input pin */
-case class SinkAnnotation(target: Named, pin: String) extends
-    SingleTargetAnnotation[Named] {
+case class SinkAnnotation(target: Named, pin: String) extends SingleTargetAnnotation[Named] {
   def duplicate(n: Named) = this.copy(target = n)
 }
 
@@ -76,8 +74,9 @@ class WiringTransform extends Transform with DependencyAPIMigration {
         (sources.size, sinks.size) match {
           case (0, p) => state
           case (s, p) if (p > 0) =>
-            val wis = sources.foldLeft(Seq[WiringInfo]()) { case (seq, (pin, source)) =>
-              seq :+ WiringInfo(source, sinks(pin), pin)
+            val wis = sources.foldLeft(Seq[WiringInfo]()) {
+              case (seq, (pin, source)) =>
+                seq :+ WiringInfo(source, sinks(pin), pin)
             }
             val annosx = state.annotations.filterNot(annos.toSet.contains)
             transforms(wis)
diff --git a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
index c220692a..5e8f8616 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
@@ -25,54 +25,54 @@ case object DecWire extends DecKind
 /** Store of pending wiring information for a Module */
 case class Modifications(
   addPortOrWire: Option[(String, DecKind)] = None,
-  cons: Seq[(String, String)] = Seq.empty) {
+  cons:          Seq[(String, String)] = Seq.empty) {
 
   override def toString: String = serialize("")
 
   def serialize(tab: String): String = s"""
-   |$tab addPortOrWire: $addPortOrWire
-   |$tab cons: $cons
-   |""".stripMargin
+                                          |$tab addPortOrWire: $addPortOrWire
+                                          |$tab cons: $cons
+                                          |""".stripMargin
 }
 
 /** A lineage tree representing the instance hierarchy in a design
   */
 @deprecated("Use DiGraph/InstanceGraph", "1.1.1")
 case class Lineage(
-    name: String,
-    children: Seq[(String, Lineage)] = Seq.empty,
-    source: Boolean = false,
-    sink: Boolean = false,
-    sourceParent: Boolean = false,
-    sinkParent: Boolean = false,
-    sharedParent: Boolean = false,
-    addPort: Option[(String, DecKind)] = None,
-    cons: Seq[(String, String)] = Seq.empty) {
+  name:         String,
+  children:     Seq[(String, Lineage)] = Seq.empty,
+  source:       Boolean = false,
+  sink:         Boolean = false,
+  sourceParent: Boolean = false,
+  sinkParent:   Boolean = false,
+  sharedParent: Boolean = false,
+  addPort:      Option[(String, DecKind)] = None,
+  cons:         Seq[(String, String)] = Seq.empty) {
 
   def map(f: Lineage => Lineage): Lineage =
-    this.copy(children = children.map{ case (i, m) => (i, f(m)) })
+    this.copy(children = children.map { case (i, m) => (i, f(m)) })
 
   override def toString: String = shortSerialize("")
 
   def shortSerialize(tab: String): String = s"""
-    |$tab name: $name,
-    |$tab children: ${children.map(c => tab + "   " + c._2.shortSerialize(tab + "    "))}
-    |""".stripMargin
+                                               |$tab name: $name,
+                                               |$tab children: ${children.map(c => tab + "   " + c._2.shortSerialize(tab + "    "))}
+                                               |""".stripMargin
 
   def foldLeft[B](z: B)(op: (B, (String, Lineage)) => B): B =
     this.children.foldLeft(z)(op)
 
   def serialize(tab: String): String = s"""
-    |$tab name: $name,
-    |$tab source: $source,
-    |$tab sink: $sink,
-    |$tab sourceParent: $sourceParent,
-    |$tab sinkParent: $sinkParent,
-    |$tab sharedParent: $sharedParent,
-    |$tab addPort: $addPort
-    |$tab cons: $cons
-    |$tab children: ${children.map(c => tab + "   " + c._2.serialize(tab + "    "))}
-    |""".stripMargin
+                                          |$tab name: $name,
+                                          |$tab source: $source,
+                                          |$tab sink: $sink,
+                                          |$tab sourceParent: $sourceParent,
+                                          |$tab sinkParent: $sinkParent,
+                                          |$tab sharedParent: $sharedParent,
+                                          |$tab addPort: $addPort
+                                          |$tab cons: $cons
+                                          |$tab children: ${children.map(c => tab + "   " + c._2.serialize(tab + "    "))}
+                                          |""".stripMargin
 }
 
 object WiringUtils {
@@ -87,12 +87,12 @@ object WiringUtils {
     val childrenMap = new ChildrenMap()
     def getChildren(mname: String)(s: Statement): Unit = s match {
       case s: WDefInstance =>
-        childrenMap(mname) = childrenMap(mname) :+( (s.name, s.module) )
+        childrenMap(mname) = childrenMap(mname) :+ ((s.name, s.module))
       case s: DefInstance =>
-        childrenMap(mname) = childrenMap(mname) :+( (s.name, s.module) )
+        childrenMap(mname) = childrenMap(mname) :+ ((s.name, s.module))
       case s => s.foreach(getChildren(mname))
     }
-    c.modules.foreach{ m =>
+    c.modules.foreach { m =>
       childrenMap(m.name) = Nil
       m.foreach(getChildren(m.name))
     }
@@ -103,7 +103,7 @@ object WiringUtils {
     */
   @deprecated("Use DiGraph/InstanceGraph", "1.1.1")
   def getLineage(childrenMap: ChildrenMap, module: String): Lineage =
-    Lineage(module, childrenMap(module) map { case (i, m) => (i, getLineage(childrenMap, m)) } )
+    Lineage(module, childrenMap(module).map { case (i, m) => (i, getLineage(childrenMap, m)) })
 
   /** Return a map of sink instances to source instances that minimizes
     * distance
@@ -114,22 +114,25 @@ object WiringUtils {
     * @return a map of sink instance names to source instance names
     * @throws WiringException if a sink is equidistant to two sources
     */
-  @deprecated("This method can lead to non-determinism in your compiler pass and exposes internal details." +
-    " Please file an issue with firrtl if you have a use case!", "Firrtl 1.4")
+  @deprecated(
+    "This method can lead to non-determinism in your compiler pass and exposes internal details." +
+      " Please file an issue with firrtl if you have a use case!",
+    "Firrtl 1.4"
+  )
   def sinksToSources(sinks: Seq[Named], source: String, i: InstanceGraph): Map[Seq[WDefInstance], Seq[WDefInstance]] = {
     // The order of owners influences the order of the results, it thus needs to be deterministic with a  LinkedHashMap.
     val owners = new mutable.LinkedHashMap[Seq[WDefInstance], Vector[Seq[WDefInstance]]]
     val queue = new mutable.Queue[Seq[WDefInstance]]
     val visited = new mutable.HashMap[Seq[WDefInstance], Boolean].withDefaultValue(false)
 
-    val sourcePaths = i.fullHierarchy.collect { case (k,v) if k.module == source =>  v }
+    val sourcePaths = i.fullHierarchy.collect { case (k, v) if k.module == source => v }
     sourcePaths.flatten.foreach { l =>
       queue.enqueue(l)
       owners(l) = Vector(l)
     }
 
     val sinkModuleNames = sinks.map(getModuleName).toSet
-    val sinkPaths = i.fullHierarchy.collect { case (k,v) if sinkModuleNames.contains(k.module) => v }
+    val sinkPaths = i.fullHierarchy.collect { case (k, v) if sinkModuleNames.contains(k.module) => v }
     // sinkInsts needs to have unique entries but is also iterated over which is why we use a LinkedHashSet
     val sinkInsts = mutable.LinkedHashSet() ++ sinkPaths.flatten
 
@@ -156,8 +159,8 @@ object WiringUtils {
 
         // [todo] This is the critical section
         edges
-          .filter( e => !visited(e) && e.nonEmpty )
-          .foreach{ v =>
+          .filter(e => !visited(e) && e.nonEmpty)
+          .foreach { v =>
             owners(v) = owners.getOrElse(v, Vector()) ++ owners(u)
             queue.enqueue(v)
           }
@@ -167,8 +170,8 @@ object WiringUtils {
       // this should fail is if a sink is equidistant to two sources.
       sinkInsts.foreach { s =>
         if (!owners.contains(s) || owners(s).size > 1) {
-          throw new WiringException(
-            s"Unable to determine source mapping for sink '${s.map(_.name)}'") }
+          throw new WiringException(s"Unable to determine source mapping for sink '${s.map(_.name)}'")
+        }
       }
     }
 
@@ -184,21 +187,24 @@ object WiringUtils {
     * @return a map of sink instance names to source instance names
     * @throws WiringException if a sink is equidistant to two sources
     */
-  private[firrtl] def sinksToSourcesSeq(sinks: Seq[Named], source: String, i: InstanceKeyGraph):
-      Seq[(Seq[InstanceKey], Seq[InstanceKey])] = {
+  private[firrtl] def sinksToSourcesSeq(
+    sinks:  Seq[Named],
+    source: String,
+    i:      InstanceKeyGraph
+  ): Seq[(Seq[InstanceKey], Seq[InstanceKey])] = {
     // The order of owners influences the order of the results, it thus needs to be deterministic with a  LinkedHashMap.
     val owners = new mutable.LinkedHashMap[Seq[InstanceKey], Vector[Seq[InstanceKey]]]
     val queue = new mutable.Queue[Seq[InstanceKey]]
     val visited = new mutable.HashMap[Seq[InstanceKey], Boolean].withDefaultValue(false)
 
-    val sourcePaths = i.fullHierarchy.collect { case (k,v) if k.module == source =>  v }
+    val sourcePaths = i.fullHierarchy.collect { case (k, v) if k.module == source => v }
     sourcePaths.flatten.foreach { l =>
       queue.enqueue(l)
       owners(l) = Vector(l)
     }
 
     val sinkModuleNames = sinks.map(getModuleName).toSet
-    val sinkPaths = i.fullHierarchy.collect { case (k,v) if sinkModuleNames.contains(k.module) => v }
+    val sinkPaths = i.fullHierarchy.collect { case (k, v) if sinkModuleNames.contains(k.module) => v }
     // sinkInsts needs to have unique entries but is also iterated over which is why we use a LinkedHashSet
     val sinkInsts = mutable.LinkedHashSet() ++ sinkPaths.flatten
 
@@ -225,8 +231,8 @@ object WiringUtils {
 
         // [todo] This is the critical section
         edges
-          .filter( e => !visited(e) && e.nonEmpty )
-          .foreach{ v =>
+          .filter(e => !visited(e) && e.nonEmpty)
+          .foreach { v =>
             owners(v) = owners.getOrElse(v, Vector()) ++ owners(u)
             queue.enqueue(v)
           }
@@ -236,8 +242,8 @@ object WiringUtils {
       // this should fail is if a sink is equidistant to two sources.
       sinkInsts.foreach { s =>
         if (!owners.contains(s) || owners(s).size > 1) {
-          throw new WiringException(
-            s"Unable to determine source mapping for sink '${s.map(_.name)}'") }
+          throw new WiringException(s"Unable to determine source mapping for sink '${s.map(_.name)}'")
+        }
       }
     }
 
@@ -249,8 +255,7 @@ object WiringUtils {
     n match {
       case ModuleName(m, _)                   => m
       case ComponentName(_, ModuleName(m, _)) => m
-      case _ => throw new WiringException(
-        "Only Components or Modules have an associated Module name")
+      case _                                  => throw new WiringException("Only Components or Modules have an associated Module name")
     }
   }
 
@@ -266,9 +271,9 @@ object WiringUtils {
   def getType(c: Circuit, module: String, comp: String): Type = {
     def getRoot(e: Expression): String = e match {
       case r: Reference => r.name
-      case i: SubIndex => getRoot(i.expr)
+      case i: SubIndex  => getRoot(i.expr)
       case a: SubAccess => getRoot(a.expr)
-      case f: SubField => getRoot(f.expr)
+      case f: SubField  => getRoot(f.expr)
     }
     val eComp = toExp(comp)
     val root = getRoot(eComp)
@@ -289,11 +294,12 @@ object WiringUtils {
       case sx: DefMemory if sx.name == root =>
         tpe = Some(MemPortUtils.memType(sx))
         sx
-      case sx => sx map getType
+      case sx => sx.map(getType)
+    }
+    val m = c.modules.find(_.name == module).getOrElse {
+      throw new WiringException(s"Must have a module named $module")
     }
-    val m = c.modules find (_.name == module) getOrElse {
-      throw new WiringException(s"Must have a module named $module") }
-    tpe = m.ports find (_.name == root) map (_.tpe)
+    tpe = m.ports.find(_.name == root).map(_.tpe)
     m match {
       case Module(i, n, ps, b) => getType(b)
       case e: ExtModule =>
@@ -301,10 +307,10 @@ object WiringUtils {
     tpe match {
       case None => throw new WiringException(s"Didn't find $comp in $module!")
       case Some(t) =>
-        def setType(e: Expression): Expression = e map setType match {
+        def setType(e: Expression): Expression = e.map(setType) match {
           case ex: Reference => ex.copy(tpe = t)
-          case ex: SubField => ex.copy(tpe = field_type(ex.expr.tpe, ex.name))
-          case ex: SubIndex => ex.copy(tpe = sub_type(ex.expr.tpe))
+          case ex: SubField  => ex.copy(tpe = field_type(ex.expr.tpe, ex.name))
+          case ex: SubIndex  => ex.copy(tpe = sub_type(ex.expr.tpe))
           case ex: SubAccess => ex.copy(tpe = sub_type(ex.expr.tpe))
         }
         setType(eComp).tpe