Stringified annotations (#367)

Restricts annotations to be string-based (and thus less typesafe)
Makes annotations more easily serializable and interact with Chisel

4 files changed, 51 insertions, 36 deletions

diff --git a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala
index d73fbc91..668bc2e5 100644
--- a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala
+++ b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala
@@ -4,7 +4,7 @@ package firrtl
 package passes
 package memlib
 import ir._
-import Annotations._
+import annotations._
 import wiring._
 
 class CreateMemoryAnnotations(reader: Option[YamlFileReader]) extends Transform {
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
index 6b56c5e8..2501ba04 100644
--- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
@@ -11,12 +11,16 @@ import firrtl.Utils.{one, zero, BoolType}
 import MemPortUtils.memPortField
 import firrtl.passes.memlib.AnalysisUtils.{Connects, getConnects, getOrigin}
 import WrappedExpression.weq
-import Annotations._
+import annotations._
 
-case class InferReadWriteAnnotation(t: String) extends Annotation with Loose with Unstable {
-  val target = CircuitName(t)
-  def duplicate(n: Named) = this.copy(t=n.name)
-  def transform = classOf[InferReadWrite]
+object InferReadWriteAnnotation {
+  def apply(t: String) = Annotation(CircuitName(t), classOf[InferReadWrite], "")
+  def apply(target: CircuitName) = Annotation(target, classOf[InferReadWrite], "")
+  def unapply(a: Annotation): Option[(CircuitName)] = a match {
+    case Annotation(CircuitName(t), transform, "") if transform == classOf[InferReadWrite] =>
+      Some(CircuitName(t))
+    case _ => None
+  }
 }
 
 // This pass examine the enable signals of the read & write ports of memories
@@ -155,6 +159,7 @@ class InferReadWrite extends Transform with PassBased {
   )
   def execute(state: CircuitState): CircuitState = getMyAnnotations(state) match {
     case Nil => CircuitState(state.circuit, state.form)
-    case Seq(InferReadWriteAnnotation(_)) => CircuitState(runPasses(state.circuit), state.form)
+    case Seq(InferReadWriteAnnotation(CircuitName(state.circuit.main))) =>
+      CircuitState(runPasses(state.circuit), state.form)
   }
 }
diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
index 30196fad..44dad557 100644
--- a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
+++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
@@ -10,18 +10,17 @@ import firrtl.Mappers._
 import MemPortUtils.{MemPortMap, Modules}
 import MemTransformUtils._
 import AnalysisUtils._
-import Annotations._
+import firrtl.annotations._
 import wiring._
 
 
 /** Annotates the name of the pin to add for WiringTransform
   */
-case class PinAnnotation(target: CircuitName, pins: Seq[String]) extends Annotation with Loose with Unstable {
-  def transform = classOf[ReplaceMemMacros]
-  def duplicate(n: Named) = n match {
-    case n: CircuitName => this.copy(target = n)
-    case _ => throwInternalError
+object PinAnnotation {
+  def apply(target: CircuitName, pins: Seq[String]): Annotation = {
+    Annotation(target, classOf[ReplaceMemMacros], pins.foldLeft("") { (str, p) => str + "pin:" + p + " " } )
   }
+  val matcher = "pin:([^ ]+)".r
 }
 
 /** Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file.
@@ -220,10 +219,11 @@ class ReplaceMemMacros(writer: ConfWriter) extends Transform {
     writer.serialize()
     val pins = getMyAnnotations(state) match {
       case Nil => Nil
-      case Seq(p) => p match {
-        case PinAnnotation(c, pins) => pins
-        case _ => error(s"Bad Annotation: ${p}")
-      }
+      case Seq(Annotation(c, t, string)) =>
+        PinAnnotation.matcher.findAllIn(string).toSeq match {
+          case Nil => error(s"Bad Annotation: ${Annotation(c, t, string)}")
+          case seq => seq
+        }
       case _ => throwInternalError
     }
     val annos = pins.foldLeft(Seq[Annotation]()) { (seq, pin) =>
diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
index 67b81160..f8f76a49 100644
--- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
+++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
@@ -5,7 +5,7 @@ package memlib
 
 import firrtl._
 import firrtl.ir._
-import Annotations._
+import firrtl.annotations._
 import AnalysisUtils._
 import Utils.error
 import java.io.{File, CharArrayWriter, PrintWriter}
@@ -64,9 +64,9 @@ class ConfWriter(filename: String) {
   }
 }
 
-case class ReplSeqMemAnnotation(t: String) extends Annotation with Loose with Unstable {
-
-  val usage = """
+object ReplSeqMemAnnotation {
+  def apply(t: String): Annotation = {
+    val usage = """
 [Optional] ReplSeqMem
   Pass to replace sequential memories with blackboxes + configuration file
 
@@ -82,18 +82,29 @@ Optional Arguments:
   -i<filename>         Specify the input configuration file (for additional optimizations)
 """    
 
-  val passOptions = PassConfigUtil.getPassOptions(t, usage)
-  val outputConfig = passOptions.getOrElse(
-    OutputConfigFileName, 
-    error("No output config file provided for ReplSeqMem!" + usage)
-  )
-  val passCircuit = passOptions.getOrElse(
-    PassCircuitName, 
-    error("No circuit name specified for ReplSeqMem!" + usage)
-  )
-  val target = CircuitName(passCircuit)
-  def duplicate(n: Named) = this copy (t = t.replace(s"-c:$passCircuit", s"-c:${n.name}"))
-  def transform = classOf[ReplSeqMem]
+    val passOptions = PassConfigUtil.getPassOptions(t, usage)
+    val outputConfig = passOptions.getOrElse(
+      OutputConfigFileName, 
+      error("No output config file provided for ReplSeqMem!" + usage)
+    )
+    val inputFileName = PassConfigUtil.getPassOptions(t).getOrElse(InputConfigFileName, "")
+    val passCircuit = passOptions.getOrElse(
+      PassCircuitName, 
+      error("No circuit name specified for ReplSeqMem!" + usage)
+    )
+    val target = CircuitName(passCircuit)
+    Annotation(target, classOf[ReplSeqMem], s"$inputFileName $outputConfig")
+  }
+
+  def apply(target: CircuitName, inputFileName: String, outputConfig: String): Annotation =
+    Annotation(target, classOf[ReplSeqMem], s"$inputFileName $outputConfig")
+
+  private val matcher = "([^ ]*) ([^ ]+)".r
+  def unapply(a: Annotation): Option[(CircuitName, String, String)] = a match {
+    case Annotation(CircuitName(c), t, matcher(inputFileName, outputConfig)) if t == classOf[ReplSeqMem] =>
+      Some((CircuitName(c), inputFileName, outputConfig))
+    case _ => None
+  }
 }
 
 class SimpleTransform(p: Pass, form: CircuitForm) extends Transform {
@@ -139,14 +150,13 @@ class ReplSeqMem extends Transform with SimpleRun {
     getMyAnnotations(state) match {
       case Nil => state.copy(annotations = None) // Do nothing if there are no annotations
       case p => (p.collectFirst { case a if (a.target == CircuitName(state.circuit.main)) => a }) match {
-        case Some(ReplSeqMemAnnotation(t)) =>
-          val inputFileName = PassConfigUtil.getPassOptions(t).getOrElse(InputConfigFileName, "")
+        case Some(ReplSeqMemAnnotation(target, inputFileName, outputConfig)) =>
           val inConfigFile = {
             if (inputFileName.isEmpty) None 
             else if (new File(inputFileName).exists) Some(new YamlFileReader(inputFileName))
             else error("Input configuration file does not exist!")
           }
-          val outConfigFile = new ConfWriter(PassConfigUtil.getPassOptions(t)(OutputConfigFileName))
+          val outConfigFile = new ConfWriter(outputConfig)
           run(state, passSeq(inConfigFile, outConfigFile))
         case _ => error("Unexpected transform annotation")
       }