diff options
| author | Schuyler Eldridge | 2020-05-01 15:07:54 -0400 |
|---|---|---|
| committer | GitHub | 2020-05-01 19:07:54 +0000 |
| commit | ee0d4079c6076b0af1f9e557f69e7346cdd89d4f (patch) | |
| tree | 8e56e51ba311c5ba9e5eb935c810cf5bb4a9eb64 /src/main/scala/firrtl/passes/memlib | |
| parent | 3b4e691bc4720e56089f424dbf5cb70403c1babc (diff) | |
Add missing invalidations to some transforms (#1541)
This adds missing invalidations to four transforms:
- ExpandConnects
- RemoveAccesses
- SplitExpressions
- VerilogMemDelays
This necessarily updates test cases which expect exact transform
orders to reflect the new order.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala index 131a198b..dd644323 100644 --- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala +++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala @@ -175,7 +175,7 @@ object VerilogMemDelays extends Pass { Dependency[SystemVerilogEmitter] ) override def invalidates(a: Transform): Boolean = a match { - case _: transforms.ConstantPropagation => true + case _: transforms.ConstantPropagation | ResolveFlows => true case _ => false } |