Rename gender to flow

The following names are changed:
  - gender        -> flow
  - Gender        -> Flow
  - MALE          -> SourceFlow
  - FEMALE        -> SinkFlow
  - BIGENDER      -> DuplexFlow
  - UNKNOWNGENDER -> UnknownFlow

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

5 files changed, 15 insertions, 15 deletions

diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
index 44f45985..1e88a9b0 100644
--- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
@@ -160,7 +160,7 @@ class InferReadWrite extends Transform with SeqTransformBased with HasShellOptio
     CheckInitialization,
     InferTypes,
     ResolveKinds,
-    ResolveGenders
+    ResolveFlows
   )
   def execute(state: CircuitState): CircuitState = {
     val runTransform = state.annotations.contains(InferReadWriteAnnotation)
diff --git a/src/main/scala/firrtl/passes/memlib/MemUtils.scala b/src/main/scala/firrtl/passes/memlib/MemUtils.scala
index bf8b9401..b16a7424 100644
--- a/src/main/scala/firrtl/passes/memlib/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemUtils.scala
@@ -29,11 +29,11 @@ object toBitMask {
     (mask.tpe, dataType) match {
       case (mt: VectorType, dt: VectorType) =>
         seqCat((0 until mt.size).reverse map { i =>
-          hiermask(WSubIndex(mask, i, mt.tpe, UNKNOWNGENDER), dt.tpe)
+          hiermask(WSubIndex(mask, i, mt.tpe, UnknownFlow), dt.tpe)
         })
       case (mt: BundleType, dt: BundleType) =>
         seqCat((mt.fields zip dt.fields) map { case (mf, df) =>
-          hiermask(WSubField(mask, mf.name, mf.tpe, UNKNOWNGENDER), df.tpe)
+          hiermask(WSubField(mask, mf.name, mf.tpe, UnknownFlow), df.tpe)
         })
       case (UIntType(width), dt: GroundType) if width == IntWidth(BigInt(1)) =>
         seqCat(List.fill(bitWidth(dt).intValue)(mask))
@@ -80,9 +80,9 @@ object MemPortUtils {
   }
 
   def memPortField(s: DefMemory, p: String, f: String): Expression = {
-    val mem = WRef(s.name, memType(s), MemKind, UNKNOWNGENDER)
+    val mem = WRef(s.name, memType(s), MemKind, UnknownFlow)
     val t1 = field_type(mem.tpe, p)
     val t2 = field_type(t1, f)
-    WSubField(WSubField(mem, p, t1, UNKNOWNGENDER), f, t2, UNKNOWNGENDER)
+    WSubField(WSubField(mem, p, t1, UnknownFlow), f, t2, UnknownFlow)
   }
 }
diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
index 6ccfd601..f3ef917b 100644
--- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
+++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
@@ -126,7 +126,7 @@ class ReplSeqMem extends Transform with HasShellOptions {
         new SimpleMidTransform(InferTypes),
         Uniquify,
         new SimpleMidTransform(ResolveKinds),
-        new SimpleMidTransform(ResolveGenders))
+        new SimpleMidTransform(ResolveFlows))
 
   def execute(state: CircuitState): CircuitState = {
     val annos = state.annotations.collect { case a: ReplSeqMemAnnotation => a }
diff --git a/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala b/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala
index b552470d..41c47dce 100644
--- a/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala
+++ b/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala
@@ -38,14 +38,14 @@ object AnalysisUtils {
   /** Find a connection LHS's origin from a module's list of node-to-node connections
     *   regardless of whether constant propagation has been run.
     * Will search past trivial primop/mux's which do not affect its origin.
-    * Limitations: 
+    * Limitations:
     *   - Only works in a module (stops @ module inputs)
     *   - Only does trivial primop/mux's (is not complete)
     * TODO(shunshou): implement more equivalence cases (i.e. a + 0 = a)
     */
   def getOrigin(connects: Connects, s: String): Expression =
-    getOrigin(connects)(WRef(s, UnknownType, ExpKind, UNKNOWNGENDER))
-  def getOrigin(connects: Connects)(e: Expression): Expression = e match { 
+    getOrigin(connects)(WRef(s, UnknownType, ExpKind, UnknownFlow))
+  def getOrigin(connects: Connects)(e: Expression): Expression = e match {
     case Mux(cond, tv, fv, _) =>
       val fvOrigin = getOrigin(connects)(fv)
       val tvOrigin = getOrigin(connects)(tv)
@@ -58,12 +58,12 @@ object AnalysisUtils {
       else e
     case DoPrim(PrimOps.Or, args, consts, tpe) if args exists (weq(_, one)) => one
     case DoPrim(PrimOps.And, args, consts, tpe) if args exists (weq(_, zero)) => zero
-    case DoPrim(PrimOps.Bits, args, Seq(msb, lsb), tpe) =>  
+    case DoPrim(PrimOps.Bits, args, Seq(msb, lsb), tpe) =>
       val extractionWidth = (msb - lsb) + 1
       val nodeWidth = bitWidth(args.head.tpe)
       // if you're extracting the full bitwidth, then keep searching for origin
       if (nodeWidth == extractionWidth) getOrigin(connects)(args.head) else e
-    case DoPrim((PrimOps.AsUInt | PrimOps.AsSInt | PrimOps.AsClock), args, _, _) => 
+    case DoPrim((PrimOps.AsUInt | PrimOps.AsSInt | PrimOps.AsClock), args, _, _) =>
       getOrigin(connects)(args.head)
     // It is a correct optimization to treat ValidIf as a connection
     case ValidIf(cond, value, _) => getOrigin(connects)(value)
diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
index 10bcadfb..335e1121 100644
--- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
+++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
@@ -15,7 +15,7 @@ import collection.mutable
 
 /** This pass generates delay reigsters for memories for verilog */
 object VerilogMemDelays extends Pass {
-  val ug = UNKNOWNGENDER
+  val ug = UnknownFlow
   type Netlist = collection.mutable.HashMap[String, Expression]
   implicit def expToString(e: Expression): String = e.serialize
   private def NOT(e: Expression) = DoPrim(Not, Seq(e), Nil, BoolType)
@@ -58,14 +58,14 @@ object VerilogMemDelays extends Pass {
         // 1) reference to the last pipe register
         // 2) pipe registers and connects
         val node = DefNode(NoInfo, namespace.newTemp, netlist(e))
-        val wref = WRef(node.name, e.tpe, NodeKind, MALE)
+        val wref = WRef(node.name, e.tpe, NodeKind, SourceFlow)
         ((0 until n) foldLeft( (wref, Seq[Statement](node)) )){case ((ex, stmts), i) =>
           val name = namespace newName s"${LowerTypes.loweredName(e)}_pipe_$i"
           val exx = WRef(name, e.tpe, RegKind, ug)
           (exx, stmts ++ Seq(DefRegister(NoInfo, name, e.tpe, clk, zero, exx)) ++
             (if (i < n - 1 && WrappedExpression.weq(cond, one)) Seq(Connect(NoInfo, exx, ex)) else {
               val condn = namespace newName s"${LowerTypes.loweredName(e)}_en"
-              val condx = WRef(condn, BoolType, NodeKind, FEMALE)
+              val condx = WRef(condn, BoolType, NodeKind, SinkFlow)
               Seq(DefNode(NoInfo, condn, cond),
                   Connect(NoInfo, exx, Mux(condx, ex, exx, e.tpe)))
             })
@@ -94,7 +94,7 @@ object VerilogMemDelays extends Pass {
         Connect(NoInfo, memPortField(mem, writer, "addr"), addr),
         Connect(NoInfo, memPortField(mem, writer, "data"), data)
       )
- 
+
       stmts ++= ((sx.readers flatMap {reader =>
         // generate latency pipes for read ports (enable & addr)
         val clk = netlist(memPortField(sx, reader, "clk"))