Wiring (#348)

Added wiring pass and simple test

4 files changed, 90 insertions, 18 deletions

diff --git a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala
new file mode 100644
index 00000000..10cc8f88
--- /dev/null
+++ b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala
@@ -0,0 +1,25 @@
+package firrtl
+package passes
+package memlib
+import ir._
+import Annotations._
+import wiring._
+
+class CreateMemoryAnnotations(reader: Option[YamlFileReader], replaceID: TransID, wiringID: TransID) extends Transform {
+  def name = "Create Memory Annotations"
+  def execute(c: Circuit, map: AnnotationMap): TransformResult = reader match {
+    case None => TransformResult(c)
+    case Some(r) =>
+      import CustomYAMLProtocol._
+      r.parse[Config] match {
+        case Seq(config) =>
+          val cN = CircuitName(c.main)
+          val top = TopAnnotation(ModuleName(config.top.name, cN), wiringID)
+          val source = SourceAnnotation(ComponentName(config.source.name, ModuleName(config.source.module, cN)), wiringID)
+          val pin = PinAnnotation(cN, replaceID, config.pin.name)
+          TransformResult(c, None, Some(AnnotationMap(Seq(top, source, pin))))
+        case Nil => TransformResult(c, None, None)
+        case _ => error("Can only have one config in yaml file")
+      }
+  }
+}
diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
index a52f7d38..9ab496d2 100644
--- a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
+++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala
@@ -10,12 +10,24 @@ import firrtl.Mappers._
 import MemPortUtils.{MemPortMap, Modules}
 import MemTransformUtils._
 import AnalysisUtils._
+import Annotations._
+import wiring._
+
+
+/** Annotates the name of the pin to add for WiringTransform
+  */
+case class PinAnnotation(target: CircuitName, tID: TransID, pin: String) extends Annotation with Loose with Unstable {
+  def duplicate(n: Named) = n match {
+    case n: CircuitName => this.copy(target = n)
+    case _ => throwInternalError
+  }
+}
 
 /** Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file.
   * This will not generate wmask ports if not needed.
   * Creates the minimum # of black boxes needed by the design.
   */
-class ReplaceMemMacros(writer: ConfWriter) extends Pass {
+class ReplaceMemMacros(writer: ConfWriter, myID: TransID, wiringID: TransID) extends Transform {
   def name = "Replace Memory Macros"
 
   /** Return true if mask granularity is per bit, false if per byte or unspecified
@@ -194,7 +206,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Pass {
        map updateStmtRefs(memPortMap))
   }
 
-  def run(c: Circuit) = {
+  def execute(c: Circuit, map: AnnotationMap): TransformResult = {
     val namespace = Namespace(c)
     val memMods = new Modules
     val nameMap = new NameMap
@@ -202,6 +214,15 @@ class ReplaceMemMacros(writer: ConfWriter) extends Pass {
     val modules = c.modules map updateMemMods(namespace, nameMap, memMods)
     // print conf
     writer.serialize()
-    c copy (modules = modules ++ memMods)
+    val pin = map get myID match {
+      case Some(p) => 
+        p.values.head match {
+          case PinAnnotation(c, _, pin) => pin
+          case _ => error(s"Bad Annotations: ${p.values}")
+        }
+      case None => "pin"
+    }
+    val annos = memMods.collect { case m: ExtModule => SinkAnnotation(ModuleName(m.name, CircuitName(c.main)), wiringID, pin) }
+    TransformResult(c.copy(modules = modules ++ memMods), None, Some(AnnotationMap(annos)))
   }  
 }
diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
index dfa828c9..01f020f5 100644
--- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
+++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
@@ -9,6 +9,7 @@ import Annotations._
 import AnalysisUtils._
 import Utils.error
 import java.io.{File, CharArrayWriter, PrintWriter}
+import wiring._
 
 sealed trait PassOption
 case object InputConfigFileName extends PassOption
@@ -92,21 +93,36 @@ Optional Arguments:
   def duplicate(n: Named) = this copy (t = t.replace(s"-c:$passCircuit", s"-c:${n.name}"))
 }
 
+case class SimpleTransform(p: Pass) extends Transform {
+  def execute(c: Circuit, map: AnnotationMap): TransformResult =
+    TransformResult(p.run(c))
+}
 class ReplSeqMem(transID: TransID) extends Transform with SimpleRun {
-  def passSeq(inConfigFile: Option[YamlFileReader], outConfigFile: ConfWriter) =
-    Seq(Legalize,
-        ToMemIR,
-        ResolveMaskGranularity,
-        RenameAnnotatedMemoryPorts,
-        ResolveMemoryReference,
-        //new AnnotateValidMemConfigs(inConfigFile),
-        new ReplaceMemMacros(outConfigFile),
-        RemoveEmpty,
-        CheckInitialization,
-        InferTypes,
-        Uniquify,
-        ResolveKinds,         // Must be run for the transform to work!
-        ResolveGenders)
+  def passSeq(inConfigFile: Option[YamlFileReader], outConfigFile: ConfWriter): Seq[Transform] =
+    Seq(SimpleTransform(Legalize),
+        SimpleTransform(ToMemIR),
+        SimpleTransform(ResolveMaskGranularity),
+        SimpleTransform(RenameAnnotatedMemoryPorts),
+        SimpleTransform(ResolveMemoryReference),
+        new CreateMemoryAnnotations(inConfigFile, TransID(-7), TransID(-8)),
+        new ReplaceMemMacros(outConfigFile, TransID(-7), TransID(-8)),
+        new WiringTransform(TransID(-8)),
+        SimpleTransform(RemoveEmpty),
+        SimpleTransform(CheckInitialization),
+        SimpleTransform(InferTypes),
+        SimpleTransform(Uniquify),
+        SimpleTransform(ResolveKinds),
+        SimpleTransform(ResolveGenders))
+  def run(circuit: Circuit, map: AnnotationMap, xForms: Seq[Transform]): TransformResult = {
+    (xForms.foldLeft(TransformResult(circuit, None, Some(map)))) { case (tr: TransformResult, xForm: Transform) =>
+      val x = xForm.execute(tr.circuit, tr.annotation.get)
+      x.annotation match {
+        case None => TransformResult(x.circuit, None, Some(map))
+        case Some(ann) => TransformResult(x.circuit, None, Some(
+          AnnotationMap(ann.annotations ++ tr.annotation.get.annotations)))
+      }
+    }
+  }
 
   def execute(c: Circuit, map: AnnotationMap) = map get transID match {
     case Some(p) => p get CircuitName(c.main) match {
@@ -118,7 +134,7 @@ class ReplSeqMem(transID: TransID) extends Transform with SimpleRun {
           else error("Input configuration file does not exist!")
         }
         val outConfigFile = new ConfWriter(PassConfigUtil.getPassOptions(t)(OutputConfigFileName))
-        run(c, passSeq(inConfigFile, outConfigFile))
+        run(c, map, passSeq(inConfigFile, outConfigFile))
       case _ => error("Unexpected transform annotation")
     }
     case _ => TransformResult(c)
diff --git a/src/main/scala/firrtl/passes/memlib/YamlUtils.scala b/src/main/scala/firrtl/passes/memlib/YamlUtils.scala
index a1088300..fcef4229 100644
--- a/src/main/scala/firrtl/passes/memlib/YamlUtils.scala
+++ b/src/main/scala/firrtl/passes/memlib/YamlUtils.scala
@@ -5,8 +5,18 @@ import java.io.{File, CharArrayWriter, PrintWriter}
 
 object CustomYAMLProtocol extends DefaultYamlProtocol {
   // bottom depends on top
+  implicit val _pin = yamlFormat1(Pin)
+  implicit val _source = yamlFormat2(Source)
+  implicit val _top = yamlFormat1(Top)
+  implicit val _configs = yamlFormat3(Config)
 }
 
+case class Pin(name: String)
+case class Source(name: String, module: String)
+case class Top(name: String)
+case class Config(pin: Pin, source: Source, top: Top)
+
+
 class YamlFileReader(file: String) {
   import CustomYAMLProtocol._
   def parse[A](implicit reader: YamlReader[A]) : Seq[A] = {