diff options
| author | Schuyler Eldridge | 2020-04-22 20:26:11 -0400 |
|---|---|---|
| committer | GitHub | 2020-04-22 20:26:11 -0400 |
| commit | 404d419a42c33ce4a68eedce636c336adf7d53be (patch) | |
| tree | 607b55e30774227895c75b60fb8fd67845ed23a8 /src/main/scala/firrtl/passes/memlib | |
| parent | 65360f886f9b92438d1b6fe609120b34ebb413cf (diff) | |
| parent | ffa6958535292d636923739d9d77b566054e2208 (diff) | |
Merge pull request #1537 from freechipsproject/optionalPrerequisitesOf
Change `dependents` to `optionalPrerequisiteOf`
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib')
6 files changed, 6 insertions, 6 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala index 48e8041a..7d537387 100644 --- a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala +++ b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala @@ -13,7 +13,7 @@ class CreateMemoryAnnotations(reader: Option[YamlFileReader]) extends Transform override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty - override def dependents = Forms.MidEmitters + override def optionalPrerequisiteOf = Forms.MidEmitters def execute(state: CircuitState): CircuitState = reader match { case None => state diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index 0de2f46d..ddcf9483 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -152,7 +152,7 @@ class InferReadWrite extends Transform override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty - override def dependents = Forms.MidEmitters + override def optionalPrerequisiteOf = Forms.MidEmitters val options = Seq( new ShellOption[Unit]( diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala index abc145f0..f14a793e 100644 --- a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala +++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala @@ -30,7 +30,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Transform with DependencyAPIM override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty - override def dependents = Forms.MidEmitters + override def optionalPrerequisiteOf = Forms.MidEmitters /** Return true if mask granularity is per bit, false if per byte or unspecified */ diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala index f5030188..fe470ef9 100644 --- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala +++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala @@ -107,7 +107,7 @@ class ReplSeqMem extends Transform with HasShellOptions with DependencyAPIMigrat override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty - override def dependents = Forms.MidEmitters + override def optionalPrerequisiteOf = Forms.MidEmitters val options = Seq( new ShellOption[String]( diff --git a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala index 007aa330..e64f6cd9 100644 --- a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala +++ b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala @@ -20,7 +20,7 @@ class ResolveMemoryReference extends Transform with DependencyAPIMigration with override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty - override def dependents = Forms.MidEmitters + override def optionalPrerequisiteOf = Forms.MidEmitters /** Helper class for determining when two memories are equivalent while igoring * irrelevant details like name and info diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala index 3da4c391..131a198b 100644 --- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala +++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala @@ -170,7 +170,7 @@ object VerilogMemDelays extends Pass { override def prerequisites = firrtl.stage.Forms.LowForm :+ Dependency(firrtl.passes.RemoveValidIf) - override val dependents = + override val optionalPrerequisiteOf = Seq( Dependency[VerilogEmitter], Dependency[SystemVerilogEmitter] ) |