diff options
| author | Albert Magyar | 2019-02-01 11:01:35 -0800 |
|---|---|---|
| committer | Adam Izraelevitz | 2019-02-01 11:01:35 -0800 |
| commit | 6b59614462ae8591db999fef9ba0d451e56d1c24 (patch) | |
| tree | 95c8ba8e9a1135fce36f24a5416a16e5e8a93263 /src/main/scala/firrtl/passes/memlib/ToMemIR.scala | |
| parent | 4e77c5e14a05cedda621a4acdbc435bed23a202d (diff) | |
Mem helpers (#1010)
* Add memory WRef factory for completeness
* Refactor DefAnnotatedMemory construction for clarity
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/ToMemIR.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/ToMemIR.scala | 15 |
1 files changed, 1 insertions, 14 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/ToMemIR.scala b/src/main/scala/firrtl/passes/memlib/ToMemIR.scala index feb6ae59..a9f4b330 100644 --- a/src/main/scala/firrtl/passes/memlib/ToMemIR.scala +++ b/src/main/scala/firrtl/passes/memlib/ToMemIR.scala @@ -19,20 +19,7 @@ object ToMemIR extends Pass { def updateStmts(s: Statement): Statement = s match { case m: DefMemory if m.readLatency == 1 && m.writeLatency == 1 && (m.writers.length + m.readwriters.length) == 1 && m.readers.length <= 1 => - DefAnnotatedMemory( - m.info, - m.name, - m.dataType, - m.depth, - m.writeLatency, - m.readLatency, - m.readers, - m.writers, - m.readwriters, - m.readUnderWrite, - None, // mask granularity annotation - None // No reference yet to another memory - ) + DefAnnotatedMemory(m) case sx => sx map updateStmts } |
