diff options
| author | Adam Izraelevitz | 2017-03-23 16:16:24 -0700 |
|---|---|---|
| committer | GitHub | 2017-03-23 16:16:24 -0700 |
| commit | 67eb4e2de6166b8f1eb5190215640117b82e8c48 (patch) | |
| tree | 18cbaf901eff58262d833bf5bc0d75262c9ab57d /src/main/scala/firrtl/passes/memlib/ToMemIR.scala | |
| parent | 4cffd184397905eeb79e2df0913b4ded97dc8558 (diff) | |
Pass now subclasses Transform (#477)
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/ToMemIR.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/ToMemIR.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/ToMemIR.scala b/src/main/scala/firrtl/passes/memlib/ToMemIR.scala index eb9d0859..feb6ae59 100644 --- a/src/main/scala/firrtl/passes/memlib/ToMemIR.scala +++ b/src/main/scala/firrtl/passes/memlib/ToMemIR.scala @@ -13,8 +13,6 @@ import firrtl.ir._ * - zero or one read port */ object ToMemIR extends Pass { - def name = "To Memory IR" - /** Only annotate memories that are candidates for memory macro replacements * i.e. rw, w + r (read, write 1 cycle delay) */ |