Reorganized memory blackboxing (#336)

* Reorganized memory blackboxing

Moved to new package memlib
Added comments
Moved utility functions around
Removed unused AnnotateValidMemConfigs.scala

* Fixed tests to pass

* Use DefAnnotatedMemory instead of AppendableInfo

* Broke passes up into simpler passes

AnnotateMemMacros ->
  (ToMemIR, ResolveMaskGranularity)
UpdateDuplicateMemMacros ->
  (RenameAnnotatedMemoryPorts, ResolveMemoryReference)

* Fixed to make tests run

* Minor changes from code review

* Removed vim comments and renamed ReplSeqMem

1 files changed, 41 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/passes/memlib/ToMemIR.scala b/src/main/scala/firrtl/passes/memlib/ToMemIR.scala
new file mode 100644
index 00000000..741ea5ef
--- /dev/null
+++ b/src/main/scala/firrtl/passes/memlib/ToMemIR.scala
@@ -0,0 +1,41 @@
+package firrtl.passes
+package memlib
+
+import firrtl.Mappers._
+import firrtl.ir._
+
+/** Annotates sequential memories that are candidates for macro replacement.
+  * Requirements for macro replacement:
+  *   - read latency and write latency of one
+  *   - only one readwrite port or write port
+  *   - zero or one read port
+  */
+object ToMemIR extends Pass {
+  def name = "To Memory IR"
+
+  /** Only annotate memories that are candidates for memory macro replacements
+    * i.e. rw, w + r (read, write 1 cycle delay)
+    */
+  def updateStmts(s: Statement): Statement = s match {
+    case m: DefMemory if m.readLatency == 1 && m.writeLatency == 1 &&
+        (m.writers.length + m.readwriters.length) == 1 && m.readers.length <= 1 =>
+      DefAnnotatedMemory(
+        m.info,
+        m.name,
+        m.dataType,
+        m.depth,
+        m.writeLatency,
+        m.readLatency,
+        m.readers,
+        m.writers,
+        m.readwriters,
+        m.readUnderWrite,
+        None, // mask granularity annotation
+        None  // No reference yet to another memory
+      )
+    case sx => sx map updateStmts
+  }
+
+  def annotateModMems(m: DefModule) = m map updateStmts
+  def run(c: Circuit) = c copy (modules = c.modules map annotateModMems)
+}