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authorSchuyler Eldridge2020-06-22 19:47:24 -0400
committerGitHub2020-06-22 19:47:24 -0400
commit8c9d8f68e038cd9e245dd66580af962267024de0 (patch)
tree30f5d068ea78caf172008f900e3d4fde7e20f6b0 /src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala
parenta845a11458fb0feed337d416ff45a503c7771bb3 (diff)
parentd66ff2357e59113ecf48c7d257edff429c4266e0 (diff)
Merge pull request #1700 from freechipsproject/deprecate-PreservesAll
Deprecate PreservesAll Trait, Remove Usages
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala')
-rw-r--r--src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala
index e64f6cd9..29200631 100644
--- a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala
+++ b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala
@@ -6,7 +6,6 @@ import firrtl._
import firrtl.ir._
import firrtl.Mappers._
import firrtl.annotations._
-import firrtl.options.PreservesAll
import firrtl.stage.Forms
/** A component, e.g. register etc. Must be declared only once under the TopAnnotation */
@@ -16,11 +15,12 @@ case class NoDedupMemAnnotation(target: ComponentName) extends SingleTargetAnnot
/** Resolves annotation ref to memories that exactly match (except name) another memory
*/
-class ResolveMemoryReference extends Transform with DependencyAPIMigration with PreservesAll[Transform] {
+class ResolveMemoryReference extends Transform with DependencyAPIMigration {
override def prerequisites = Forms.MidForm
override def optionalPrerequisites = Seq.empty
override def optionalPrerequisiteOf = Forms.MidEmitters
+ override def invalidates(a: Transform) = false
/** Helper class for determining when two memories are equivalent while igoring
* irrelevant details like name and info