diff options
| author | Schuyler Eldridge | 2020-04-22 19:55:32 -0400 |
|---|---|---|
| committer | GitHub | 2020-04-22 19:55:32 -0400 |
| commit | 65360f886f9b92438d1b6fe609120b34ebb413cf (patch) | |
| tree | 073ebe73d43e652af1f71a08d34cc30a421c4dbb /src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala | |
| parent | 8653fd628f83c1bcb329dd37844ddfdb8f4cf206 (diff) | |
| parent | 184d40095179a9f49dd21e73e2c02b998bac5c00 (diff) | |
Merge pull request #1534 from freechipsproject/deprecate-transform-2
Trait-base Dependency API Migration
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala index b0d3731f..007aa330 100644 --- a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala +++ b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala @@ -6,6 +6,8 @@ import firrtl._ import firrtl.ir._ import firrtl.Mappers._ import firrtl.annotations._ +import firrtl.options.PreservesAll +import firrtl.stage.Forms /** A component, e.g. register etc. Must be declared only once under the TopAnnotation */ case class NoDedupMemAnnotation(target: ComponentName) extends SingleTargetAnnotation[ComponentName] { @@ -14,9 +16,11 @@ case class NoDedupMemAnnotation(target: ComponentName) extends SingleTargetAnnot /** Resolves annotation ref to memories that exactly match (except name) another memory */ -class ResolveMemoryReference extends Transform { - def inputForm = MidForm - def outputForm = MidForm +class ResolveMemoryReference extends Transform with DependencyAPIMigration with PreservesAll[Transform] { + + override def prerequisites = Forms.MidForm + override def optionalPrerequisites = Seq.empty + override def dependents = Forms.MidEmitters /** Helper class for determining when two memories are equivalent while igoring * irrelevant details like name and info |
