diff options
| author | Schuyler Eldridge | 2019-09-16 19:03:37 -0400 |
|---|---|---|
| committer | GitHub | 2019-09-16 19:03:37 -0400 |
| commit | f93e1d240f80848dc12c25906239fe6c8a4d42b5 (patch) | |
| tree | 9b39634fc4bd5044e37939a0bd568ae4ed158826 /src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala | |
| parent | 7e39ea8ec948ff1db7ccd0d850923a86d2d8a4e7 (diff) | |
| parent | b3dd7924f27342083681be6dd5932ef95d354029 (diff) | |
Merge pull request #1124 from freechipsproject/gender-to-flow
Gender to Flow
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala b/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala index b552470d..41c47dce 100644 --- a/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala +++ b/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala @@ -38,14 +38,14 @@ object AnalysisUtils { /** Find a connection LHS's origin from a module's list of node-to-node connections * regardless of whether constant propagation has been run. * Will search past trivial primop/mux's which do not affect its origin. - * Limitations: + * Limitations: * - Only works in a module (stops @ module inputs) * - Only does trivial primop/mux's (is not complete) * TODO(shunshou): implement more equivalence cases (i.e. a + 0 = a) */ def getOrigin(connects: Connects, s: String): Expression = - getOrigin(connects)(WRef(s, UnknownType, ExpKind, UNKNOWNGENDER)) - def getOrigin(connects: Connects)(e: Expression): Expression = e match { + getOrigin(connects)(WRef(s, UnknownType, ExpKind, UnknownFlow)) + def getOrigin(connects: Connects)(e: Expression): Expression = e match { case Mux(cond, tv, fv, _) => val fvOrigin = getOrigin(connects)(fv) val tvOrigin = getOrigin(connects)(tv) @@ -58,12 +58,12 @@ object AnalysisUtils { else e case DoPrim(PrimOps.Or, args, consts, tpe) if args exists (weq(_, one)) => one case DoPrim(PrimOps.And, args, consts, tpe) if args exists (weq(_, zero)) => zero - case DoPrim(PrimOps.Bits, args, Seq(msb, lsb), tpe) => + case DoPrim(PrimOps.Bits, args, Seq(msb, lsb), tpe) => val extractionWidth = (msb - lsb) + 1 val nodeWidth = bitWidth(args.head.tpe) // if you're extracting the full bitwidth, then keep searching for origin if (nodeWidth == extractionWidth) getOrigin(connects)(args.head) else e - case DoPrim((PrimOps.AsUInt | PrimOps.AsSInt | PrimOps.AsClock), args, _, _) => + case DoPrim((PrimOps.AsUInt | PrimOps.AsSInt | PrimOps.AsClock), args, _, _) => getOrigin(connects)(args.head) // It is a correct optimization to treat ValidIf as a connection case ValidIf(cond, value, _) => getOrigin(connects)(value) |