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authorAdam Izraelevitz2018-02-22 17:25:55 -0800
committerGitHub2018-02-22 17:25:55 -0800
commit46b78943a726e4c9bf85ffb25a2ccf926b10dda7 (patch)
tree39f9363400fdd39e2e55f3dc8c5221461941edec /src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala
parent65bbf155003a86cd836f7ff4a2def6af91794780 (diff)
Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, but not Emitter. (#717)
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala')
-rw-r--r--src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala b/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala
index 79ecd9cd..0424b1dd 100644
--- a/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala
+++ b/src/main/scala/firrtl/passes/memlib/ResolveMaskGranularity.scala
@@ -77,7 +77,7 @@ object AnalysisUtils {
/** Checks whether the two memories are equivalent in all respects except name
*/
- def eqMems(a: DefAnnotatedMemory, b: DefAnnotatedMemory, noDeDupeMems: Seq[String]) =
+ def eqMems(a: DefAnnotatedMemory, b: DefAnnotatedMemory, noDeDupeMems: Seq[String]): Boolean =
a == b.copy(info = a.info, name = a.name, memRef = a.memRef) &&
!(noDeDupeMems.contains(a.name) || noDeDupeMems.contains(b.name))
}
@@ -120,6 +120,6 @@ object ResolveMaskGranularity extends Pass {
case sx => sx map updateStmts(connects)
}
- def annotateModMems(m: DefModule) = m map updateStmts(getConnects(m))
- def run(c: Circuit) = c copy (modules = c.modules map annotateModMems)
+ def annotateModMems(m: DefModule): DefModule = m map updateStmts(getConnects(m))
+ def run(c: Circuit): Circuit = c copy (modules = c.modules map annotateModMems)
}