diff options
| author | Albert Magyar | 2018-11-26 16:19:44 -0800 |
|---|---|---|
| committer | GitHub | 2018-11-26 16:19:44 -0800 |
| commit | beba4398edeb67624ad010b7ee13f8b863f8478f (patch) | |
| tree | a5b7a875a48b6c0426502aa14a0c664c375f8978 /src/main/scala/firrtl/passes/memlib/MemUtils.scala | |
| parent | 27afc3d8defd9e2a85d5e3d2f9d2b35310b9b775 (diff) | |
Make return types of util functions more specific (#949)
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/MemUtils.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/MemUtils.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemUtils.scala b/src/main/scala/firrtl/passes/memlib/MemUtils.scala index 709e57af..9328dfe4 100644 --- a/src/main/scala/firrtl/passes/memlib/MemUtils.scala +++ b/src/main/scala/firrtl/passes/memlib/MemUtils.scala @@ -63,7 +63,7 @@ object MemPortUtils { ) // Todo: merge it with memToBundle - def memType(mem: DefMemory): Type = { + def memType(mem: DefMemory): BundleType = { val rType = BundleType(defaultPortSeq(mem) :+ Field("data", Flip, mem.dataType)) val wType = BundleType(defaultPortSeq(mem) ++ Seq( |