diff options
| author | Albert Magyar | 2019-09-12 17:06:01 -0700 |
|---|---|---|
| committer | Albert Magyar | 2019-09-30 16:22:01 -0700 |
| commit | 082bc994457cc5f6780b58fb914a6ab3eb8a021f (patch) | |
| tree | c0998198ebc9036308754826ffb863e43259f3fa /src/main/scala/firrtl/passes/memlib/MemUtils.scala | |
| parent | 01399dd00ba18b1e4d5c1f773ca33f077c53c534 (diff) | |
Implement read-first memories in VerilogMemDelays
* Corrects behavior under write collisions
* Avoids heavily refactoring pass
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/MemUtils.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/MemUtils.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemUtils.scala b/src/main/scala/firrtl/passes/memlib/MemUtils.scala index b16a7424..bb441ebb 100644 --- a/src/main/scala/firrtl/passes/memlib/MemUtils.scala +++ b/src/main/scala/firrtl/passes/memlib/MemUtils.scala @@ -79,7 +79,7 @@ object MemPortUtils { (mem.readwriters map (Field(_, Flip, rwType)))) } - def memPortField(s: DefMemory, p: String, f: String): Expression = { + def memPortField(s: DefMemory, p: String, f: String): WSubField = { val mem = WRef(s.name, memType(s), MemKind, UnknownFlow) val t1 = field_type(mem.tpe, p) val t2 = field_type(t1, f) |